The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

A Review of NBTI Degradation and its Impact on the Performance of SRAM

“…NBTI degradation results in increasing the absolute value of the threshold voltage of the PMOS device which in turn leads to the reduction in the drain current, transconductance and mobility. It has been observed that the effect of NBTI becomes more severe because of the introduction of nitrogen into the gate dielectric which is done primarily to reduce the boron penetration from P+ poly gate into the thin oxide and also for reducing the gate leakage [5]. Criterion for the device failure is still a debatable topic, Schroder et al [6] proposed that device failure criteria is often benchmarked at v th shift of 50 mV or ΔI ds /I ds ~ 10% but still it is circuit dependent.…”

A dual-core 64-bit ultraSPARC microprocessor for dense server applications

“…NBTI is the aging effect that decreases PMOS current mainly due to shift over the silicon lifetime [10], [11]. This shift is strongly dependent on gate-source bias and temperature but barely dependent on drain voltage.…”

Implications of Negative Bias Temperature Instability in Power MOS Transistors

“…NBTI effects are manifested as the changes in device threshold voltage (V T ), transconductance (g m ) and drain current (I D ), and have been observed mostly in p-channel MOSFETs operated under negative gate oxide fields in the range 2 -6 MV/cm at temperatures around 100°C or higher (Huard et al, 2006;Stathis & Zafar, 2006;Schroder, 2005;Alam & Mahapatra, 2005;Schroder & Babcock, 2003;Kimizuka et al, 1999;Ogawa et al, 1995). The phenomenon itself had been known for many years, but only recently has been recognised as a serious reliability issue in state-of-the-art MOS integrated circuits.…”

“…The amounts of NBT stress-induced oxide-trapped charge and interface traps in n-and p-channel devices are generally similar (Stathis & Zafar, 2006), but above consideration clearly shows that the net effect on threshold voltage, ΔV T , must be greater for p-channel devices, because in this case the positive oxide charge and positive interface charge are additive. As for the question on the role of stress bias polarity, it seems well established that holes are necessary to initiate and/or enhance the bias temperature stress degradation (Huard et al, 2006;Stathis & Zafar, 2006;Schroder, 2005;Alam & Mahapatra, 2005;Schroder & Babcock, 2003;Kimizuka et al, 1999;Ogawa et al, 1995), which provides straight answer since only negative gate bias can provide holes at the SiO 2 /Si interface. Moreover, this is an additional reason why the greatest impact of NBTI occurs in p-channel transistors since only those devices experience a uniform negative gate bias condition during typical CMOS circuit operation.…”

“…Several models of microscopic mechanisms responsible for the observed degradation have been proposed (Huard et al, 2006;Stathis & Zafar, 2006;Schroder, 2005;Alam & Mahapatra, 2005;Schroder & Babcock, 2003;Ogawa et al, 1995), but in spite of very extensive studies in recent years, the mechanisms of NBTI phenomenon are still not fully understood, so technology optimization to minimize NBTI is still far from being achieved. With reduction in gate oxide thickness, NBT stress-induced threshold voltage shifts are getting more critical and can put serious limit to a lifetime of p-channel devices having gate oxide thinner than 3.5 nm (Kimizuka et al, 1999), so accurate models and well established procedure for lifetime estimation are needed to make good prediction of device reliable operation. Though the gate oxide in nanometre scale technologies is continuously being thinned down, there is still high interest in ultra-thick oxides owing to widespread use of MOS technologies for the realisation of power devices.…”