The IBM z900 decimal arithmetic unit

Busaba, F.Y.; Krygowski, C. A.; Li, W.H.; Schwarz, E.; Carlough, S.R.

doi:10.1109/acssc.2001.987708

Cited by 71 publications

(38 citation statements)

References 4 publications

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“…A restoring divider selects the next positive quotient digit 0 ≤ +1 ≤ 9 such that the next partial residual is as small as possible but still positive. The IBM z900 architecture, for instance, implements such a decimal restoring divider [19]. By contrast, the QDS function of a decimal nonrestoring divider uses a digit set that is positive as well as negative − ≤ +1 ≤ , and the partial residual .…”

Section: Digit Recurrence Divisionmentioning

confidence: 99%

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Baesler

Voigt

2013

International Journal of Reconfigurable Computing

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Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carrypropagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.

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Section: Digit Recurrence Divisionmentioning

confidence: 99%

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Baesler

Voigt

2013

International Journal of Reconfigurable Computing

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“…The decimal unit has many enhancements over the last generation unit [6]. The current decimal unit includes a 16 digit BCD adder/subtractor with sign insertion, conversion tables to convert between binary and BCD arithmetic formats and other support logic to perform packing and unpacking between BCD, ASCII and Unicode formats.…”

Section: Decimal Assist Unitmentioning

confidence: 99%

The design of the fixed point unit for the z990 microprocessor

Busaba

Slegel

Carlough

et al. 2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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The paper presents the design of the Fixed Point Unit (FXU) for the IBM eServer z990 microprocessor (announced in 2Q '03) that runs at 1.2 GHz [2]. The FXU is capable of executing two Register-Memory instructions including arithmetic instructions and a branch instruction in a single cycle. The FXU executes a total of 369 instructions that operate on variable size operands (1 to 256 bytes). The instruction set include decimal arithmetic with multiplies and divides, binary arithmetic, shifts and rotates, loads/stores, branches, long moves, logical operations, convert instructions, and other special instructions. The FXU consists of 64-bit dataflow stack that is custom designed and a control stack that is synthesized. The current FXU is the first superscalar design for the CMOS z-series machines, has a new improved decimal unit, and has for the first time a 16x64 bit binary multiplier.

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“…The G-P functions may be computed according to Figure 6, using the outputs of the mod 16 stage, including the carry-out s 4 . With more hardware consumption, but saving time delays, formulas (18) may be used.…”

Section: Base-10 Carry-chain Addersmentioning

confidence: 99%

“…Performances required by applications with intensive decimal arithmetic are not met by most of the conventional software-based decimal arithmetic libraries [1]. Hardware implementation embedded in recently commercialized general purpose processors [3,4] is gaining importance.…”

Section: Introductionmentioning

confidence: 99%

High-Speed FPGA 10's Complement Adders-Subtractors

Bioul

Vázquez

Deschamps

et al. 2010

International Journal of Reconfigurable Computing

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This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands.

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The IBM z900 decimal arithmetic unit

Cited by 71 publications

References 4 publications

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

The design of the fixed point unit for the z990 microprocessor

High-Speed FPGA 10's Complement Adders-Subtractors

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