The Hierarchically Tiled Arrays programming approach

Abstract

In this paper, we show our initial experience with a class of objects, called Hierarchically Tiled Arrays (HTAs), that encapsulate parallelism. HTAs allow the construction of single-threaded parallel programs where a master process distributes tasks to be executed by a collection of servers holding the components (tiles) of the HTAs. The tiled and recursive nature of HTAs facilitates the adaptation of the programs that use them to varying machine configurations, and eases the mapping of data and tasks to parallel computers with a hierarchical organization. We have implemented HTAs as a MATLAB TM toolbox, overloading conventional operators and array functions such that HTA operations appear to the programmer as extensions of MATLAB TM . Our experiments show that the resulting environment is ideal for the prototyping of parallel algorithms and greatly improves the ease of development of parallel programs while providing reasonable performance.

Runnemede: An architecture for Ubiquitous High-Performance Computing

“…Our higher-level models include Hierarchically-Tiled Arrays (HTAs) [13], which expresses computations as blocks or tiles in successive, hierarchical levels, and Concurrent Collections (CnC) [7], which describes computations in a high-level dataflow-like manner. The R-Stream R compiler can automatically generate parallelized and locally-optimized code for sequential loop nests.…”

Collective Memory Transfers for Multi-Core Chips

“…HTAs are a polyhedral representation language that compactly and efficiently expresses distributed tile arrays [22]. The declaration of HTAs includes how the distributed array is tiled and how the tiles map to processors.…”

“…For the CMS API we adopt the HTA syntax [22] to define a 2D plane of data that a CMS operation handles. We also modify the simple HTA syntax to compactly express ghost zones by adding a parameter to denote the number of ghost zone cells in each dimension.…”

“…In this paper, we demonstrate a hardware approach to coordinating on-chip data movement named collective memory scheduling (CMS), and the programming constructs to make access to this capability efficient and easy to express using the hierarchically tiled array (HTA) abstraction [22,26]. CMS coordinates processors such that distributed data arrays are read from or written to the DRAM as a unit, and transfered to or from the appropriate processors.…”

“…• Modifies the HTA representation [22,26] which defines distributed data arrays and their mapping to processors, to simplify the application programming interface (API) since the same collective function call is made by all processors, with no need to calculate individual DMA address ranges, as in STI Cell [62]. While CMS can use alternative software constructs, HTAs simplify the programming interface.…”