The hierarchical method of synthesis of large-capacity comparators with the use of programmable logic integrated circuits

Designing of Hierarchical Structures for Binary Comparators on FPGA/SoC

“…This work is a continuation of researches to find the effective design methods for binary comparators based on a programmable logic [17,18,19,20]. In [17], the following methods of the comparator synthesis are considered: parallel, sequential, parallelsequential, and with adder using.…”

“…In [18], the method of the comparator design in the form of a hierarchical structure is offered. The experimental researches are executed by Altera MAX+PLUS II platform.…”

“…In [18,19,20], the methods of designing comparators generally on 64 bits were considered. In [18], for researches the outdated MAX+PLUS II platform and the AHDL language that supported only by Altera tools was used.…”

“…In [18,19,20], the methods of designing comparators generally on 64 bits were considered. In [18], for researches the outdated MAX+PLUS II platform and the AHDL language that supported only by Altera tools was used. In [18,19], the lpm_compare function and the AHDL language were used to implement comparators of the first level.…”

“…In [18], for researches the outdated MAX+PLUS II platform and the AHDL language that supported only by Altera tools was used. In [18,19], the lpm_compare function and the AHDL language were used to implement comparators of the first level. Besides, the graphics editor of Quartus II platform was used to design hierarchical structures of comparators.…”