We address the problem of computing critical area for open faults (opens) in a circuit layout in the presence of multilayer loops and redundant interconnects. The extraction of critical area is the main computational bottleneck in predicting the yield loss of a VLSI design due to random manufacturing defects. We first model the problem as a geometric graph problem and we solve it efficiently by exploiting its geometric nature. To model open faults we formulate a new geometric version of the classic min-cut problem in graphs, termed the geometric min-cut problem. Then the critical area extraction problem gets reduced to the construction of a generalized Voronoi diagram for open faults, based on concepts of higher order Voronoi diagrams. The approach expands the Voronoi critical area computation paradigm [5, 16-19, 22, 28] with the ability to accurately compute critical area for missing material defects even in the presence of loops and redundant interconnects spanning over multiple layers. The generalized Voronoi diagrams used in the solution are combinatorial structures of independent interest.
Report Info
Published
June 2010Number USI-INF-TR-2010-6
Institution
Faculty of Informatics Università della Svizzera italiana Lugano, SwitzerlandOnline Access www.inf.usi.ch/techreports
IntroductionCatastrophic yield loss of integrated circuits is caused to a large extent by random particle defects interfering with the manufacturing process resulting in functional failures such as open or short circuits. Yield loss due to random manufacturing defects has been studied extensively in both industry and academia and several yield models for random defects have been proposed (see e.g., [8,25,26]). The focus of all models is the concept of critical area, a measure reflecting the sensitivity of a design to random defects during manufacturing. Reliable critical area extraction is essential for today's IC manufacturing especially when DFM (Design for Manufacturability) initiatives are under consideration. The critical area of a circuit layout on a layer A is defined aswhere A(r ) denotes the area in which the center of a defect of radius r must fall in order to cause a circuit failure and D(r ) is the density function of the defect size. The defect density function has been estimated as follows [8,12,25,29]:where p,q are real numbers (typically p = 3,q = 1), c = (q + 1)(p − 1)/(q + p ), and r 0 is some minimum optically resolvable size. Using typical values for p,q , and c , the widely used defect size distribution is derived, 1