The HARMONIA Project: Hardware Monitoring for Automotive Systems-of-Systems

Nguyen, Thang; Bartocci, Ezio; Ničković, Dejan; Grosu, Radu; Jakšić, Stefan; Selyunin, Konstantin

doi:10.1007/978-3-319-47169-3_28

Cited by 10 publications

(8 citation statements)

References 19 publications

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“…Such additional information may be useful to take some corrective action before the actual violation occurs. Runtime monitoring mechanisms have been applied in different domains for instance in safety-critical embedded systems such as automotive systems [11] and robotic applications such as the NASA K9 Rover [9]. In the domain of network security, a monitor can be used as a firewall or a Network Intrusion Detection (NID), that monitors network traffic to detect (and prevent) some denial-of-service (DoS) attacks.…”

Section: Introductionmentioning

confidence: 99%

Predictive runtime verification of timed properties

Pinisetty

Jéron

Tripakis

et al. 2017

Journal of Systems and Software

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Runtime verification (RV) techniques are used to continuously check whether the (untrustworthy) output of a black-box system satisfies or violates a desired property. When we consider runtime verification of timed properties, physical time elapsing between actions influences the satisfiability of the property. This paper introduces predictive runtime verification of timed properties where the system is not entirely a black-box but something about its behaviour is known a priori. A priori knowledge about the behaviour of the system allows the verification monitor to foresee the satisfaction (or violation) of the monitored property. In addition to providing a conclusive verdict earlier, the verification monitor also provides additional information such as the minimum (maximum) time when the property can be violated (satisfied) in the future. The feasibility of the proposed approach is demonstrated by a prototype implementation, which is able to synthesize predictive runtime verification monitors from timed automata.

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Section: Introductionmentioning

confidence: 99%

Predictive runtime verification of timed properties

Pinisetty

Jéron

Tripakis

et al. 2017

Journal of Systems and Software

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“…Ideally, a single method would have been used, but both approaches were used by different teams in the competition. Monitoring hardware In the last decade, the increasing complexity of the circuit design has been making their verification and validation more convenient to perform using hardware emulation instead of the classical simulation, a task becoming very time consuming and expensive for the industry [57,72].…”

Section: Lessons Learned and Discussionmentioning

confidence: 99%

“…FoCs [35] developed by IBM and MBAC [25][26][27] [57,58,72,79] propose several practical techniques for generating FieldProgrammable Gate Array (FPGA) hardware monitors for Signal Temporal Logic (STL), an extension of MTL handling predicates over the real-values.…”

Section: Lessons Learned and Discussionmentioning

confidence: 99%

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Bartocci

Falcone

Bonakdarpour

et al. 2017

Int J Softw Tools Technol Transfer

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The first international Competition on Runtime Verification (CRV) was held in September 2014, in Toronto, Canada, as a satellite event of the 14th international conference on Runtime Verification (RV'14). The event was organized in three tracks: (1) offline monitoring, (2) online monitoring of C programs, and (3) online monitoring of Java programs. In this paper, we report on the phases and rules, a description of the participating teams and their submitted benchmark, the (full) results, as well as the lessons learned from the competition.

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“…In the case of softwarebased instrumentation, it can operate at the level of the source (language) of the application system, its intermediate representation (IR), the binary, or using library interposition. Hardware-based instrumentation [8,9,75,99] can be for instance realized by observing and controlling the system through a JTAG port and using dedicated hardware (e.g., an FPGA).…”

Section: Deploymentmentioning

confidence: 99%

On the Runtime Enforcement of Timed Properties

Falcone

Pinisetty

2019

Runtime Verification

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Runtime enforcement refers to the theories, techniques, and tools for enforcing correct behavior of systems at runtime. We are interested in such behaviors described by specifications that feature timing constraints formalized in what is generally referred to as timed properties. This tutorial presents a gentle introduction to runtime enforcement (of timed properties). First, we present a taxonomy of the main principles and concepts involved in runtime enforcement. Then, we give a brief overview of a line of research on theoretical runtime enforcement where timed properties are described by timed automata and feature uncontrollable events. Then, we mention some tools capable of runtime enforcement, and we present the TiPEX tool dedicated to timed properties. Finally, we present some open challenges and avenues for future work.

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The HARMONIA Project: Hardware Monitoring for Automotive Systems-of-Systems

Cited by 10 publications

References 19 publications

Predictive runtime verification of timed properties

Predictive runtime verification of timed properties

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

On the Runtime Enforcement of Timed Properties

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