The Gmicro/100 32-bit microprocessor

Yoshida, Toyohiko; Shimisu, T.; Mizugaki, S.; Hinata, J.

doi:10.1109/40.85722

Cited by 14 publications

(1 citation statement)

References 12 publications

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“…The GlOOFTS includes a 32-bit microprocessor Gmicro/lOO [3] and a supportmodule for fault-tolerant operations. The Gmicro/lOO is based on the TRON specifications [4].…”

Section: Introductionmentioning

confidence: 99%

Self-checking and recovering microprocessor G100FTS for fault-tolerant systems

Terayama

Korematsu

Kitamura

et al.

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

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This paper describes the architecture and implementation of the application specific processor, the GlOOFTS, designed for faulttolerant systems. The GlOOFTS integrates the core-processor and the support module for fault-tolerant operation. The core-processor is the 32-bit microprocessor Gmicro/lOO based on the TRON specifications. The support module provides a mechanism of error detection, a rollback operation that recovers a processor from a transient fault, diagnosis of faulty processors, and reconfiguration of a single processor system to make it operate continuously. The GlOOFTS drastically reduces the component count of a system, and provides high system reliability. The GlOOFTS performs all the fault-tolerant operations in hardware and requires no dedicated programs for fault-tolerance. The chip contains 805K transistors withim a chip size of 13 mm x 14 nun. A 1.0-micron, double metal CMOS technology has been used.

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“…The GlOOFTS includes a 32-bit microprocessor Gmicro/lOO [3] and a supportmodule for fault-tolerant operations. The Gmicro/lOO is based on the TRON specifications [4].…”

Section: Introductionmentioning

confidence: 99%

Self-checking and recovering microprocessor G100FTS for fault-tolerant systems

Terayama

Korematsu

Kitamura

et al.

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

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The Gmicro/500 superscalar microprocessor with branch buffers

et al. 1993

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A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface

Matsuo

Kondo

Takata

et al.

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

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This paper describes a 32-bit CISC superscalar microprocessor designed for high-end embedded applications, such as X-window terminals and printers. To realize high performance of processing a series of m e m o r y data such as aflame buffer and a character-string, we have used block-data-transfer and 64-bit processing to improve execution e&iency of multiple-operation instructions of the processor. 16-byte block readlwrite operations through a 32-bit external data bus have accomplished high bandwidth for DRAM access, even in the case of noncacheable regions such as a frame buffer. In executing multiple-operation instructions, 64-bit processing has been realized by operating the dual execution circuits for superscalar executions and a @-bit internal data bus under the control of a very long micro-instruction word. By using these techniques, we have enhanced the frame buffer manipulation performance of this processor 1.5 to 2 times.

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The Gmicro/100 32-bit microprocessor

Cited by 14 publications

References 12 publications

Self-checking and recovering microprocessor G100FTS for fault-tolerant systems

Self-checking and recovering microprocessor G100FTS for fault-tolerant systems

The Gmicro/500 superscalar microprocessor with branch buffers

A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface

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