The Fluent Abstract Machine.

Ranade, Abhiram; Bhatt, Sandeep N.; Johnsson, Lennart

doi:10.21236/ada327476

Cited by 48 publications

(19 citation statements)

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“…With the message format as above, it is possible for each node to send outgoing message packets as soon as the corresponding packets arrive on all incoming edges. In fact message combining can also be made to work with pipelining [30,31].…”

Section: Variable-length Messagesmentioning

confidence: 99%

Randomized Routing and Sorting on Fixed-Connection Networks

Leighton

Maggs

Ranade

et al. 1994

Journal of Algorithms

110

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This paper presents a general paradigm for the design of packet routing algorithms for fixed-connection networks. Its basis is a randomized on-line algorithm for scheduling any set of N packets whose paths have congestion c on any bounded-degree leveled network with depth L in O(c + L + log N ) steps, using constant-size queues. In this paradigm, the design of a routing algorithm is broken into three parts: (1) showing that the underlying network can emulate a leveled network, (2) designing a path selection strategy for the leveled network, and (3) applying the scheduling algorithm. This strategy yields randomized algorithms for routing and sorting in time proportional to the diameter for meshes, butterflies, shuffle-exchange graphs, multidimensional arrays, and hypercubes. It also leads to the construction of an area-universal network: an N -node network with area Θ(N ) that can simulate any other network of area O(N ) with slowdown O(log N ).

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Section: Variable-length Messagesmentioning

confidence: 99%

Randomized Routing and Sorting on Fixed-Connection Networks

Leighton

Maggs

Ranade

et al. 1994

Journal of Algorithms

110

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“…At programming language level this makes possible to use shared variables and eliminates the need for lockings and atomic operations unless the program declares asynchronous tasks at high level in purpose [21] [22]. Past attempts to realize a PRAM include the omega network-based NYU Ultracomputer [31], CEDAR [16] and IBM Research Parallel Processor Prototype (RP3) [28], butterfly-based Fluent machine [29], 3D torus-based Cray MTA supercomputer [2] and its successors MTA2 and XMT provided by Cray, multiport memory-based solution [4], and butterfly-based SB-PRAM [1,22]. Unfortunately, these attempts have been mainly unsuccessful due to sub-optimal solutions, like non-scalable interconnect topologies, inefficient co-exploitation of multiple levels parallelism, sub-optimal shared memory emulation algorithms, and out-dated prototyping technologies.…”

Section: Introductionmentioning

confidence: 99%

A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads

Forsell¹

2011

IJNC

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It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy parallel programmability crucial to wider penetration of CMPs to general purpose computing. This implementation relies on exploitation of the slack of parallel applications to hide the latency of the memory system instead of caches, sufficient bisection bandwidth to guarantee high throughput, and hashing to avoid hot spots in intercommunication. Unfortunately this solution can not handle workloads with low thread-level parallelism (TLP) efficiently because then there is not enough parallel slackness available for hiding the latency. In this paper we show that integrating non-uniform memory access (NUMA) support to the PRAM implementation architecture can solve this problem and provide a natural way for migration of the legacy code written for a sequential or multi-core NUMA machine. The obtained PRAM-NUMA hybrid model is defined and architectural implementation of it is outlined on our ECLIPSE ESM CMP framework. A high-level programming language example is given.

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“…1 MP3D is not present in the SPLASH 2 benchmark suite [16] Various combinations of address hashing, combining and multithreading are used in machines like the NYU ultracomputer [8,11], the Fluent Machine [12], Cray T3D [1], TERA [5] and the SB-PRAM [2].…”

Section: Introduction and Previous Workmentioning

confidence: 99%

Performance of MP3D on the SB-PRAM Prototype

Dementiev

Klein

Paul

2002

Euro-Par 2002 Parallel Processing

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Abstract. The SB-PRAM is a shared memory machine which hides latency by simple interleaved context switching and which can be expected to behave almost exactly like a PRAM if all threads can be kept busy. We report measured run times of various versions of the MP3D benchmark on the completed hardware of a 64 processor SB-PRAM. The main findings of these experiments are: 1) parallel efficiency is 79% for 32 processors and 56% for 64 processors. 2) Parallel efficiency is limited by the number of available threads. 3) Run time overhead in the SB-PRAM network and in the memory modules due to congestion is less that 1%.

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The Fluent Abstract Machine.

Cited by 48 publications

References 0 publications

Randomized Routing and Sorting on Fixed-Connection Networks

Randomized Routing and Sorting on Fixed-Connection Networks

A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads

Performance of MP3D on the SB-PRAM Prototype

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