The First Thorough Side-Channel Hardware Trojan

Ender, Maik; Ghandali, Samaneh; Moradi, Amir; Paar, Christof

doi:10.1007/978-3-319-70694-8_26

Cited by 24 publications

(16 citation statements)

References 55 publications

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“…Our first-order secure implementation should therefore be combined with hiding countermeasures, such as random shuffling and noise modules. As an example we refer to [24], where the design of such a noise generator on the same FPGA type is given. A combination of lowering the SNR and restricting the number of encryptions performed with the same key should be able to avoid higher-order attacks in practice.…”

Section: Discussionmentioning

confidence: 99%

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

2020

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The effort in reducing the area of AES implementations has largely been focused on application-specific integrated circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on field-programmable gate arrays (FPGAs). A similar discrepancy holds for masking schemes-a well-known side-channel analysis countermeasure-which are commonly optimized to achieve minimal area in ASICs. In this paper, we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction in the area footprint on FPGA devices. We present new AES implementations which improve on the state-of-the-art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Güneysu at ASAP 2016. We further explore the protection of such implementations against side-channel attacks. We introduce a generic methodology for masking any n-bit Boolean functions of degree t with protection order d. The methodology is exact for first-order and heuristic for higher orders. Its application to our new construction of the AES S-box allows us to improve previous results and introduce the smallest first-order masked AES implementation on Xilinx FPGAs, to date.

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Section: Discussionmentioning

confidence: 99%

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

2020

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“…Reference [32] demonstrates how easy it is to insert an HT which induces side-channel leakage to recover a key once triggered. This Trojan is inserted by modifying a few gates during manufacturing to increase path delay.…”

Section: Hardware Trojan Based Side-channel Attacksmentioning

confidence: 99%

Hardware Security in IoT Devices with Emphasis on Hardware Trojans

Sidhu

Mohd

Hayajneh

2019

JSAN

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Security of IoT devices is getting a lot of attention from researchers as they are becoming prevalent everywhere. However, implementation of hardware security in these devices has been overlooked, and many researches have mainly focused on software, network, and cloud security. A deeper understanding of hardware Trojans (HTs) and protection against them is of utmost importance right now as they are the prime threat to the hardware. This paper emphasizes the need for a secure hardware-level foundation for security of these devices, as depending on software security alone is not adequate enough. These devices must be protected against sophisticated attacks, especially if the groundwork for the attacks is already laid in devices during design or manufacturing process, such as with HTs. This paper will discuss the stealthy nature of these HT, highlight HT taxonomy and insertion methods, and provide countermeasures.

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“…In such cases, adding noise modules would surely help to harden higher-order attacks. As an example we refer to [EGMP17], where the design of such a noise generator on the same FPGA type is given.…”

Section: Sca Evaluationmentioning

confidence: 99%

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES

Meyer

Moradi

Wegener

2018

TCHES

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The effort in reducing the area of AES implementations has largely been focused on Application-Specific Integrated Circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naïve implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs.In this paper we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction of the area footprint on FPGA devices. We present new AES implementations which improve on the state of the art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Güneysu at ASAP 2016. We further explore the protection of such implementations against first-order side-channel analysis attacks. Targeting the small area footprint on FPGAs, we introduce a heuristic-based algorithm to find a masking of a given function with d + 1 shares. Its application to our new construction of the AES S-box allows us to introduce the smallest masked AES implementation on Xilinx FPGAs, to-date.

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The First Thorough Side-Channel Hardware Trojan

Cited by 24 publications

References 55 publications

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

Hardware Security in IoT Devices with Emphasis on Hardware Trojans

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES

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