The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals

“…In direct down-conversion receivers, for example, the blockers are more than an octave away from the desired signal after down-conversion. Clockprogrammable discrete-time analog filters [1,25] or any other analog filtering with sufficient programmability for a filter corner can achieve this. A few of the possible approaches to solving the bottleneck with the RF front end for a multi-band receiver are discussed below.…”

Precise Delay Alignment Between Amplitude and Phase/Frequency Modulation Paths in a Digital Polar Transmitter

“…The resulting architecture will probably be more robust by producing a low phase noise and spurious degradation of the transmitter chain and low noise figure of the receiver chain in the face of millions of active logic gates on the same silicon die, as proven in [6] and [7], respectively, for 90-nm CMOS. Additionally, the new architecture would be highly reconfigurable with analog blocks that are controlled by software to guarantee the best achievable performance and parametric yield.…”

Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop

“…It is used in two fundamentally different ways: (1) as a demodulator, where it is implemented to follow phase or frequency modulation [19,20] or (2) to track a carrier or synchronizing signal which may vary in frequency with time, that is, as a local oscillator (LO) or as a clock generator [21][22][23]. Operating as a demodulator has been thought in the early 1970s [24,25] and thereabout the performance as a near-optimum FM Demodulator [26].…”