The European BOOM Project: Silicon Photonics for High-Capacity Optical Packet Routers

Stampoulidis, L.; Vyrsokinos, K.; Voigt, K.; Zimmermann, Lars; Gomez-Agis, Fausto; Dorren, H.J.S.; Sheng, Zhen; Thourhout, Dries Van; Moerl, L.; Kreissl, J.; Sedighi, Behnam; Scheytt, J. Christoph; Pagano, A.; Riccardi, E.

doi:10.1109/jstqe.2009.2038238

Cited by 17 publications

(8 citation statements)

References 25 publications

(29 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Conventionally, the integration of III-V semiconductors with silicon is based on heteroepitaxial growth of multi-layered structures on silicon or direct wafer bonding technology [6]. Different compound semiconductors (quantum dots, nanowires, thin films) heterogeneously integrated onto a silicon substrate have been intensively studied [7,8]. Devices made of such structures combine the high carrier mobility and high luminescence efficiency of III-V semiconductors with the well-developed silicon technology [9].…”

Section: Introductionmentioning

confidence: 99%

InP nanocrystals on silicon for optoelectronic applications

Prucnal

Zhou

et al. 2012

Nanotechnology

View full text Add to dashboard Cite

One of the solutions enabling performance progress, which can overcome the downsizing limit in silicon technology, is the integration of different functional optoelectronic devices within a single chip. Silicon with its indirect band gap has poor optical properties, which is its main drawback. Therefore, a different material has to be used for the on-chip optical interconnections, e.g. a direct band gap III-V compound semiconductor material. In the paper we present the synthesis of single crystalline InP nanodots (NDs) on silicon using combined ion implantation and millisecond flash lamp annealing techniques. The optical and microstructural investigations reveal the growth of high-quality (100)-oriented InP nanocrystals. The current-voltage measurements confirm the formation of an n-p heterojunction between the InP NDs and silicon. The main advantage of our method is its integration with large-scale silicon technology, which allows applying it for Si-based optoelectronic devices.

show abstract

Section: Introductionmentioning

confidence: 99%

InP nanocrystals on silicon for optoelectronic applications

Prucnal

Zhou

et al. 2012

Nanotechnology

View full text Add to dashboard Cite

show abstract

“…The all-optical wavelength conversion concept is based on the chirp filtering technique and requires a single SOA to induce chirp and two cascaded delay interferometers (Figure 5a). The full functionality is described in detail in [16]. Figure 5b) shows the device blueprint.…”

Section: All-optical Wavelength Convertermentioning

confidence: 99%

“…The total size of the chip (including the test structure) is 12x32 mm 2 . Error-free operation of this wavelength converter scheme at 160 Gb/s line rate has been reported in [16]. The wavelength converter requires <3W of electrical power consumption, including the power to drive the SOA, control the chip temperature and tune the phase shifters by a full FSR.…”

Section: All-optical Wavelength Convertermentioning

confidence: 99%

Hybrid photonic integrated circuits for faster and greener optical communication networks

Stampoulidis¹,

Kehayas²,

Zimmermann

2011

Integrated Optics: Devices, Materials, and Technologies XV

View full text Add to dashboard Cite

We present current development efforts on hybrid photonic integration for new generation "faster and greener" Tb/scapacity optical networks. On the physical layer, we present the development of a versatile, silicon-based photonic integration platform that acts as a technology "blender" bringing together different material systems including III-V and silicon-based semiconductors. The platform is also used to implement the so-called O-to-O (optical-to-optical) functionalities by patterning low-loss passive components such as MMI couplers and delay interferometers. With these passive building blocks as well as the ability for hybrid assembly of active material, we demonstrate the fabrication of key optical transport and routing devices such as optical demodulators and all-optical wavelength converters. These devices can now be used to fabricate chip-scale 100 GbE transceiver PICs and Tb/s-capacity wavelength switching platforms.

show abstract

“…It has been proven that frame assembly can increase the average IP link utilization by a factor of 2 [5], reduce the header processing complexity inside core routers by at least two orders of magnitude and reduce the energy consumption of related line cards by 30% [6]. Since the logical and memory hardware in all-optical packet networks is immature, frame assembly is even more important in reducing the core router's processing burden and implementation complexity in such networks [7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Frame Assembly and Scheduling on Edge Routers in Fixed-Size Frame-Switching Networks

Zhang

Sun

2012

J. Opt. Commun. Netw.

View full text Add to dashboard Cite

Frame assembly is seen as an important technology in future core networks since it can mitigate the ever-increasing packet header processing load on network nodes. Since frame assembly changes the pattern of traffic entering the network, it has a significant impact on such aspects of network performance as packet drop probability and end-to-end delay. This paper focus on the packet drop and delay performance on assembly nodes, sometimes called edge routers. We reveal that frame assembly on edge routers is in fact a tradeoff between packet loss performance and fairness, especially when the input client traffic is non-uniformly distributed among multiple destinations. We evaluate existing frame assembly and scheduling algorithms and try to cope with the assembly and scheduling process holistically by proposing a new algorithm, named highest efficiency fair queuing. Simulation results show that the proposed algorithm provides better performance in terms of delay and jitter, while also minimizing the average packet loss rate. . He serves on panels for four journals and 12 conferences, including IEEE JLT, OFC, APOC. His interests are in optical transport networks with GMPLS control, and optical packet switching. He is the co-author of over 200 peer-reviewed journal and conference papers.

show abstract

The European BOOM Project: Silicon Photonics for High-Capacity Optical Packet Routers

Cited by 17 publications

References 25 publications

InP nanocrystals on silicon for optoelectronic applications

InP nanocrystals on silicon for optoelectronic applications

Hybrid photonic integrated circuits for faster and greener optical communication networks

Frame Assembly and Scheduling on Edge Routers in Fixed-Size Frame-Switching Networks

Contact Info

Product

Resources

About