The Epsilon dataflow processor

Grafe, V.G.; Davidson, George S.; Hoch, James E.; Holmes, Victor P.

doi:10.1145/74925.74930

Cited by 44 publications

(11 citation statements)

References 7 publications

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“…Unfortunately, this is often difficult with the standard Von Neumman approach to computing, motivating aggressive research on alternative models such as TRIPS [17,19] and Raw [25]. A popular alternative was the DataFlow model, where instructions can execute as soon as they have their input operands available [7,6,10,9,18], instead of following the program order. Although dataflow ideas are in use, e.g., in Tomasulo's algorithm [24] actual DataFlow machines were never popular.…”

Section: Introductionmentioning

confidence: 99%

Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations

Marzulo¹,

França²,

Costa³

2008

2008 20th International Symposium on Computer Architecture and High Performance Computing

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The WaveScalar is the first DataFlow Architecture that can efficiently provide the sequential memory semantics required by imperative languages. This work presents an alternative memory ordering mechanism for this architecture, the Transaction WaveCache. Our mechanism maintains the execution order of memory operations within blocks of code, called Waves, but adds the ability to speculatively execute, out-of-order, operations from different waves. This ordering mechanism is inspired by progress in supporting Transactional Memories. Waves are considered as atomic regions and executed as nested transactions. If a wave has finished the execution of all its memory operations, as soon as the previous waves are committed, it can be committed. If a hazard is detected in a speculative Wave, all the following Waves (children) are aborted and re-executed. We evaluate the WaveCache on a set artificial benchmarks. If the benchmark does not access memory often, we could achieve speedups of around 90%. Speedups of 33.1% and 24% were observed on more memory intensive applications, and slowdowns up to 16% arise if memory bandwidth is a bottleneck. For an application full of WAW, WAR and RAW hazards, a speedup of 139.7% was verified.

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Section: Introductionmentioning

confidence: 99%

Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations

Marzulo¹,

França²,

Costa³

2008

2008 20th International Symposium on Computer Architecture and High Performance Computing

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“…I-structures [6]. On the other hand, asynchronous transfer of control (context switching) is notoriously expensive on current machines, leading many researchers to examine asynchronous parallel execution models through the study of real machines [11,13,15,22,25,27], paper architectures [1, 5, 14, 16, 1 9 ], and abstract machines [21]. In all of these proposals, the scheduling of threads is viewed as a property of the machine, invisible to the compiler.…”

Section: Introductionmentioning

confidence: 99%

Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Culler¹,

Sah²,

Schauser³

et al. 1991

SIGOPS Oper. Syst. Rev.

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In this paper, we present a relatively primitive execution model for ne-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is dened by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for eective register use under quasi-dynamic scheduling.A prototype TAM instruction set, TL0, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring ne-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors.Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such as proposed dataow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specic hardware support or merely an appropriate compilation strategy and program representation.

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“…As máquinas dinâmicas (Shimada et al, 1986;Gurd et al, 1985;Kishi et al, 1983;Grafe et al, 1989;Papadopoulos e Culler, 1990) são uma evolução das máquinas estáticas, por nelas permitirem que mais de um token esteja presente em um arco, o que significa utilizar toda a potencialidade da programação a fluxo de dados, exigindo, no entanto um tratamento mais complexo na implementação do sistema, pois é preciso além de armazenar os dados, identificar os parceiros dos dados que disparam uma operação.…”

Section: Capítulo 3 Máquinas a Fluxo De Dadosunclassified

ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados

Correia¹

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À Deus, por ter me dado saúde, capacidade, persistência e sabedoria para realizar este trabalho. Ao meu orientador prof. Dr. Jorge Luiz e Silva, que por seus conselhos, incentivo e constante bom humor, se tornou mais do que um orientador, um amigo. Agradeço pelo apoio dado nesta conquista. Aos amigos do LabES e LCR, pela amizade, compreensão e ajuda ao longo do mestrado. À todos professores que contribuíram para minha formação acadêmica. À minha família, pelo apoio incondicional dado em todas as etapas de minha vida. À minha noiva, Alexandra, amiga e companheira incansável, fonte de carinho e força nos momentos mais difíceis. Pessoa fundamental na minha trajetória e na concretização deste trabalho. Agradaço a todas as pessoas que diretamente ou indiretamente contribuíram para o desenvolvimento deste trabalho. Ao CNPq pelo apoio financeiro.

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The Epsilon dataflow processor

Cited by 44 publications

References 7 publications

Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations

Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations

Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados

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