The Effects of Varying Tilt Angle of Halo Implant on the Performance of Sub 100nm LAC MOSFETs

Sarkar,; Mallik,; Rao, V. Ramgopal

doi:10.1109/iciinfs.2006.347132

Cited by 1 publication

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“…Thin gate oxide leads to direct tunnelling with exponential increase in gate leakage current [9]- [11]. This also results in high power dissipation which ultimately degrades device performance and stability.…”

Section: Introductionmentioning

confidence: 99%

Comparative Study of Nanoscale FinFET Structures for High-K Gate Dielectrics

Parihar

Narendar

Mishra

2014

2014 International Conference on Devices, Circuits and Communications (ICDCCom)

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The MOSFET device performance deteriorates when it is scaled down to 45nm node and an alternative device structure being studied. FinFETs are the alternative new device structure, which replaces the MOSFET. The comparative study of Double Gate MOSFET (DGMOSFET), Tri-gate Fin Field Effect Transistor (FinFET) and Gate All Around (GAA) FinFET structures has been done for 22nm and 16nm technologies. The study is based on the ground of logic performance parameters which are I on /I off current ratio, Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold voltage (V t ) roll-off. These parameters are also termed as Short Channel Effects (SCEs) and for a nanoscale device performance these parameters needs to be controlled. The parameters are evaluated for various high-k dielectric materials. The high-κ dielectric Hafnium oxide (HfO 2 ) exhibits the best material to minimize SCEs for GAA structures. The aforementioned devices are also tested for transconductance (g m ) which is an analog performance parameter. The accuracy of the results has been verified by 3-D SILVACO ATLAS.

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Section: Introductionmentioning

confidence: 99%