The effects of hydroxyl-free polystyrene buffer layer on electrical performance of pentacene-based thin-film transistors with high-k oxide gate dielectric

Study on post-deposition annealing influenced contribution of hole and electron trapping to threshold voltage stability in organic field effect transistors

“…Hysteresis in transfer characteristics can be seen for both the devices, as also observed for as deposited CuPc film in our previous study (data not shown here) [10]. It is well known that silanol groups on the surface of SiO 2 can act as traps causing hysteresis [4,16]. It is also suggested in the literature that oxygen and water molecules from ambient can diffuse through the film to the dielectric/semiconductor interface and cause hysteresis [11,12].…”

“…Since OFETs are generally working in accumulation regime and most of the modulated charge lies close to the semiconductor/dielectric interface within the first few nm, the molecular ordering of the active layer at the interface is crucial for improvement in mobility as well as threshold voltage instability. Several techniques that have been employed to improve the ordering of these films are 1) varying the deposition parameters of semiconducting materials, like substrate temperature, deposition rate [1], 2) post-deposition annealing of active materials [2], 3) suitable treatment of the inorganic dielectric with self assembled monolayers (SAM) [3] or polymer films [4]. Though there are several reports on the effect of dielectric modification, the effect of post-deposition annealing on the performance of OFETs has been scarcely studied and show widely varying results.…”

“…If polarization or mobile ions in dielectric cause hysteresis, it is known to be in clockwise direction while traps at semiconductor itself mostly cause anticlockwise hysteresis [5]. Many studies show that modifying the dielectric with suitable polymer layer minimizes the number of hydroxyl groups at the interface thus reducing the trap sites and hysteresis [4]. Post-deposition annealing of semiconducting films is also shown to result in lesser instability after encapsulation of films under inert atmosphere [2] while some reports mention the return of hysteresis in OFETs when exposed to atmosphere [6].…”

Influence of active layer thickness on contribution of hole and electron trapping to threshold voltage instability in organic field effect transistors

“…Though there are a few studies on the effect of active layer thickness on mobility of charge carriers [7,8] there are only negligible studies on the role of the same in determining hysteresis in transfer characteristics and on bias stress instability [9][10][11] while many focus on the effect of silanol (Si-OH) groups at dielectric/semiconductor interface on hysteresis [12]. Girolamo et al [10] have studied the influence of active layer thickness on bias stress instability of sexithiophene based OFETs by measuring drain current decay under gate voltage stressing.…”

“…To our knowledge, the few reports that discuss the effect of active layer thickness on hysteresis do not mention about the influence of same on deciding the extent of holes and electron trapping effect causing threshold voltage instability. Generally, different methods like a) passivating the hydroxyl groups at dielectric/semiconductor interface and/or b) improving the morphology and crystallinity of semiconductor layer by modifying deposition conditions/post deposition annealing etc., are employed to minimize hysteresis [5,12,14,15]. Since electron and hole trapping are predominantly minimized by the former and latter methods respectively [5,16], a prior knowledge of influence of active layer thickness on hole and electron trapping individually is essential so that suitable methods for improvement can be employed for the thickness used.…”