The effect of silicide on ESD performance

Notermans, Guido; Heringa, A.; Dort, M. van; Jansen, S.; Kuper, F.G.

doi:10.1109/relphy.1999.761607

Cited by 32 publications

(8 citation statements)

References 10 publications

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“…9 and 10), SCG and DCG spacing plays a very important role in determining the homogeneous triggering [9], [10], blocking the silicide on both sides of the device increases the width utilization and, therefore, . The silicide blocking on the source side introduces emitter-ballasting resistance to the , which improves its stability by preventing current runaway [11] in agreement with previous work [12]. Importantly, it was observed that as the SCG spacing increased, the failure mode changed from drain-to-source to drain-to-gate [13], [14].…”

Section: B Esd Experimental Resultssupporting

confidence: 77%

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

Salman

Gauthier

Stadler

et al. 2002

IEEE Trans. Device Mater. Relib.

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In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/ npn protection devices in a 0.13-m CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 m) devices fail because of source/drain filamentation, whereas longer (0.3 m) devices with thin (22 A) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on 2 . Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device.

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Section: B Esd Experimental Resultssupporting

confidence: 77%

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

Salman

Gauthier

Stadler

et al. 2002

IEEE Trans. Device Mater. Relib.

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“…As is well known, the ESD strength of silicided technology is lower than that of nonsilicided devices due to either the reduction in emitter efficiency [3] or early current localization associated with the reduced series resistance [16], which has also been verified in this work. EMMI analysis shows that different bipolar turned-on widths can be obtained depending on the substrate and gate-bias conditions at a given ESD current level.…”

Section: Implications For the Design Of Esd Protectionsupporting

confidence: 76%

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

Duvvury

Banerjee

et al. 2002

IEEE Trans. Electron Devices

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This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width ( ) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current ( 2 ) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.Index Terms-Deep-submicron CMOS, electrostatic discharges, ESD protection, nonuniform electrostatic discharge current distribution, single-finger NMOS.

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“…However, HBM ESD levels of the LVTp-n-p devices in the 0.25-µm salicided CMOS process are lower than those of the LVTp-n-p devices in the 0.35-µm polycided CMOS process under positive-to-VSS ESD-stress condition for the multifinger layout style. The silicided diffusion in the 0.25-µm salicided CMOS process causes degradation on ESD robustness of the LVTp-n-p device drawn in multifinger layout style [14]. Under ESD-stress condition, the silicide diffusion on the device will cause the current to be crowded on the surface of the device and the heat will be located in the local area.…”

Section: Multifinger Layout Style For Lvtp-n-p To Improve Esd Robumentioning

confidence: 99%

ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS

Ker

Chang

2005

IEEE Trans. Device Mater. Relib.

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Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces with the low-voltage-triggered p-n-p (LVTp-n-p) device in CMOS technology is proposed. The LVTp-n-p, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the p-n-p device, is designed to protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The LVTp-n-p devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-µm CMOS process have proven that the ESD level of the proposed LVTp-n-p is higher than that of the traditional p-n-p device. Furthermore, layout on LVTp-n-p device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35-and 0.25-µm CMOS processes have proven that the ESD levels of the LVTp-n-pdrawn in the multifinger layout style are higher than that drawn in the single-finger layout style. Moreover, one of the LVTp-n-p devices drawn with the multifinger layout style has been used to successfully protect the input stage of an asymmetric digital subscriber line (ADSL) IC in a 0.25-µm salicided CMOS process.Index Terms-Electrostatic discharge (ESD), human body mode (HBM), low-voltage-triggered p-n-p (LVTp-n-p), optical-beaminduced resistance change (OBIRCH), photon emission microscope (EMMI).

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The effect of silicide on ESD performance

Cited by 32 publications

References 10 publications

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS

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