The effect of DC offset on current operated relays

Stringer, N.T.

doi:10.1109/icps.1997.596025

Cited by 17 publications

(10 citation statements)

References 7 publications

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“…B. DC bias effect on trip/alarm When a fault occurs in a power system, a DC offset will appear due to the inductance and resistance of the system components. The effect of the DC offset was investigated earlier in [13]. The first few cycles, the current value increases, but after the DC component attenuates, the current becomes constant.…”

Section: Fig 5 500 a Fault Simulationmentioning

confidence: 99%

Development of test facility for compatibility and performance testing of all-digital protection systems connected to IEC 61850-9-2 standard

Kucuksari

Karady

2009

2009 IEEE Power &Amp; Energy Society General Meeting

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The development of Intelligent Electronic Devices (IED) have increased the use of digital protection systems, in which the digitized signals replaced the usage of conventional analog signals. The digitized signals are generated at electronic instrument transformers and they are transferred to protection systems over a process bus based on IEC 61850-9-2 standard. This transferring process between electronic instrument transformers and protection systems requires a detailed performance evaluation, analysis, and compatibility of the two different systems, since various vendors' instrument transformers and relays are aimed to be connected. This paper presents a developed test facility for all-digital protection system performance evaluations. Typical power system faults are regenerated with the facility and the performance of the digital systems are investigated. The compatibility of an optical current transformer and a digital relay is analyzed. Digital relay's inverse time delay characteristics are obtained. Results show that alldigital systems provided by different manufacturers can work together and are suitable to protect power systems where protection is needed.

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Section: Fig 5 500 a Fault Simulationmentioning

confidence: 99%

Development of test facility for compatibility and performance testing of all-digital protection systems connected to IEC 61850-9-2 standard

Kucuksari

Karady

2009

2009 IEEE Power &Amp; Energy Society General Meeting

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“…Voltage and current instantaneous signals measured at the point of monitoring are crucial for further processes that include detection of disturbance based on accurate phasor estimation and generation of appropriate trip signals for circuit breakers. However, the estimations are affected by the addition of natural response of system elements, which forms the DC offset and high‐frequency transient components [1]. A lot of research work has been carried out in the literature about DC offset detection and removal [2–4].…”

Section: Introductionmentioning

confidence: 99%

Assessment of DC offset in fault current signal for accurate phasor estimation considering current transformer response

Achlerkar

Panigrahi

2019

IET Science, Measurement & Technology

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“…There are several reasons for the presence DO in the grid voltage including grid faults [30], analogue-to-digital conversions [31], measurement device limitations, half wave rectification (generating DC component), geomagnetic phenomena, injection of DC from RES systems, saturation of current transformer [32], sine wave asymmetries because of non-uniform characteristics of semiconductor devices etc. [33][34][35].…”

Section: Introductionmentioning

confidence: 99%

Design of an advanced PLL for accurate phase angle extraction under grid voltage HIHs and DC offset

Ali

Christofides

Hadjidemetriou

et al. 2018

IET Power Electronics

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The presence of dc offset and harmonics/interharmonics in grid voltage input signal of phaselocked loop (PLL) results in inaccurate controller response. The inaccuracies are due to the low and high frequency oscillations that appear in the PLL estimated phase, amplitude and frequency. The importance of DC offset and harmonic/interharmonic rejection capability for PLLs can be appreciated by international standards that impose strict limitations for grid-tied converters. The suppression of fundamental frequency oscillations caused by DC offset in the input signal must be carried out without compromising the dynamic response of the system. The use of low pass filters for example results in undesirable, slow response. This paper proposes an accurate and fast decoupling of fundamental frequency oscillations using a mathematic cancellation decoupling cell. Higher frequency oscillations generated by harmonics/interharmonics are eliminated by a different compensation network (HCN) that is also proposed in this paper. The performance of conventional techniques is limited because they eliminate only specifically selected harmonics. The proposed HCN module, however, eliminates any number of harmonics/interharmonics present in the grid with the least computational complexity and without any prior knowledge. Furthermore, its advanced features provide accurate synchronization under any abnormal grid condition at the lowest computational complexity when compared to existing state-of-the-art PLLs. The advanced performance of the proposed Harmonic-Interharmonic-DC-Offset (HIHDO) PLL is verified through simulation and experimental results.

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The effect of DC offset on current operated relays

Cited by 17 publications

References 7 publications

Development of test facility for compatibility and performance testing of all-digital protection systems connected to IEC 61850-9-2 standard

Development of test facility for compatibility and performance testing of all-digital protection systems connected to IEC 61850-9-2 standard

Assessment of DC offset in fault current signal for accurate phasor estimation considering current transformer response

Design of an advanced PLL for accurate phase angle extraction under grid voltage HIHs and DC offset

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