The effect of context switches on cache performance

Mogul, Jeffrey C.; Borg, Anita

doi:10.1145/106972.106982

Cited by 123 publications

(24 citation statements)

References 28 publications

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“…This OS activity causes cache misses directly and also indirectly in the applications by displacing the state of the applications from the cache. In work based on application-only simulations, Mogul and Borg [13] and Gupta el rzl [9] show the importance of preserving and reusing the cache state of applications. Given all these previous observations, our goal in this paper is to provide an indepth experintentaf characterization of the cache performance of a multiprocessor OS.…”

Section: Introductionmentioning

confidence: 99%

Characterizing the caching and synchronization performance of a multiprocessor operating system

Torrellas¹,

Gupta²,

Hennessy³

1992

Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems

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Good cache memory performance is essential to achieving high CPU utilization in shared-memory multiprocessors.While the performance of caches is determined by both application end operating system (OS ) references, most research has focused on the cache performance of applications afone. This is partiafly due to the difficulty of measuring OS activity and as a resrtl~the cache performance of the OS is largely unknown. In this paper, we characterize the cache performance of a commercial System V UNIX rtrttrtittg on a four-CPU multiprocessor.The related issue of the performance impact of the OS synchronization activity is tdso stttdicd. For our study, we use a hardware monitor that records the cache misses in the machine without perturbing it. We study three multiprocessor workloads: a parallel Compilq a multiprogrsmmed load and a commercial database. Our results show that OS misses occur frequently enough to stall CPUS for 17-21 'Yoof their non-idle time.Further, if we include application misses induced by OS interference in the cache, then the SQU time reaches 25%. A detailed analysis reveals three major sources of OS misses: instruction fetehea, process migratiom and data accesses in block operations. As for synchronization behavior, we find that OS syncfrrordzation has low overhead if supported correctly end that OS locks show good locality and low contention.

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Section: Introductionmentioning

confidence: 99%

Characterizing the caching and synchronization performance of a multiprocessor operating system

Torrellas¹,

Gupta²,

Hennessy³

1992

Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Each such migration incurs overhead, similar to a context switch [2], [3], [4], [5], from saving and restoring processor states and virtual machine control stucture (VMCS), extra translation lookaside buffer (TLB) misses and related page walks, cache misses, and interrupt rerouting (for VMs). The indirect overhead of TLB and cache misses for a migration is potentially higher than for a context switch, because the migrated thread begins execution in a totally different processor environment and cache hierarchy.…”

Section: A Motivationmentioning

confidence: 99%

“…A lot of research has been done in understanding the overhead of context switching in a computer system [2], [3], [4], [5], [7]. Context switching introduces two types of overheads in computation.…”

Section: Background and Related Workmentioning

confidence: 99%

Reducing Migration-induced Cache Misses

Reza

Byrd

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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In a large multiprocessor server platform, using multicore chips, the scheduler often migrates a scheduling entity, i.e. a thread or process or virtual machine, in order to achieve better load balancing or ensure fairness. The migration impact is likely to be more severe in virtualized environments, where high over-subscription of logical CPUs is very common for server consolidation workloads or virtual desktop infrastructure deployment. We demonstrate the performance benefit of saving and restoring cached data during migration. In particular, we measure the efficiency (benefit per cache block) of saving various subsets of the cached data, in order to balance implementation cost and complexity with improvements in cycle time. We also describe an implementation that moves cached data when a thread migrates, and we show the benefits in terms of reduced misses and reduced processor cycles.

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“…However, when this information is lost there is a cost to warm these structures again; for example, the L1 cache contents associated with our process are essentially flushed with the migration. This forces the per-core cache to be repopulated, adding to our migration overhead [32].…”

Section: Simulating Migrationmentioning

confidence: 99%

A cross-layer approach to heterogeneity and reliability

Williams¹,

Sanyal²,

Upton³

et al. 2009

2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design

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As modern hardware becomes increasingly complex, it becomes more difficult to create efficient software for common computing workloads. One way to manage this complexity is to employ holistic solutions that consider multiple layers of hardware and software in conjunction, allowing software to adapt and react to changing conditions at run time. This paper focuses on lightweight modifications to commodity hardware that enable virtual execution environments to help solve problems in the areas of power, reliability, security, and performance. We present our experimental simulation framework, which enables us to explore the design space of hardware/software collaboration, and we demonstrate its ability to produce simplified, reactive solutions to two emerging computing problems. First, we improve heterogeneous process migration with hardware feedback, and second, we use hardware information to respond to voltage emergencies (di/dt) in software. These symbiotic design approaches illustrate the simple nature yet significant potential of cross-layer, reactive solutions.

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The effect of context switches on cache performance

Cited by 123 publications

References 28 publications

Characterizing the caching and synchronization performance of a multiprocessor operating system

Characterizing the caching and synchronization performance of a multiprocessor operating system

Reducing Migration-induced Cache Misses

A cross-layer approach to heterogeneity and reliability

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