The effect of bias and load impedance to non linearity characteristics of RF LD-MOSFET

Abstract

LD MOSFET as large signal RF power amplifier has been characterized and modeled for high power and broadband RF amplifier. Large signal model has been derived and verified based on I-V characteristics and S-parameter data. Non-linier model has been used to model LD MOSFET large signal characteristics. Good fit of measured and simulation results of LD MOSFET I-V characteristics as well as S-parameter curves verified large signal model and extracted model parameters. The effect of transistor biases, V GS and V DS to 2nd (IM2) and 3rd order (IM3) intermodulation distortion of LD-MOSFET (D2081UK) relative to fundamental output power have been obtained and verified. Highest level of IM3 was shown at V GS = 1,6 V near threshold voltage (V TH = 1,4 V) and minimum level of IM3 at V GS = 2 V, at input power, P in , of -30 dBm and load impedance, R L = 50 Ω. While the effect of V DS shows maximum of IM3 at knee voltage and declining level at higher V DS . The effect of varying load impedance, R L , to IM3, IM2 and fundamental levels has shown minimum dip of IM3 at R L = 31 Ω with gradual increase as load increasing above 50 Ω. The intersection point of 3rd order intermodulation (IP3) at V GS = 2.2V shows higher power level of IP3=50dBm with input power of 18dB than level at V GS = 1.8V with IP3 of 46dBm. This behaviour of non-linearity effect of the transistor was verified and evaluated based on the large signal model of LD MOSFET device. Analysis of non-liniearity behavior based on LD MOSFET device structure and physics was carried out in comprehending the origin of non-linearity and in the implementation of linearization method.