The effect of a width transition on the electromigration reliability of Cu interconnects

Hau-Riege, Christine; Klein, R.

doi:10.1109/relphy.2008.4558915

Cited by 17 publications

(4 citation statements)

References 8 publications

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“…Indeed, voiding should not happen at a current density divergence site, but with divergence of copper flow, as explained by [20]. Electromigration diffusion in copper damascene is assumed to be dominated by the copper/capping layer and secondarily by the grain-boundary path [7].…”

Section: A Voiding Site Always Under Tsvmentioning

confidence: 99%

Resistance increase due to electromigration induced depletion under TSV

Frank

Chappaz

Leduc

et al. 2011

2011 International Reliability Physics Symposium

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Section: A Voiding Site Always Under Tsvmentioning

confidence: 99%

Resistance increase due to electromigration induced depletion under TSV

Frank

Chappaz

Leduc

et al. 2011

2011 International Reliability Physics Symposium

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“…5.16(a). This result is expected and it agrees with the observations in literature[132][133][134]. A further reduction of 2.80% is observed inFig.…”

supporting

confidence: 94%

3D electromigration modeling at the circuit layout level

He¹

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Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) in the interconnects has now become the dominant failure mechanism that determines the circuit reliability. To model the EM reliability of the interconnects in ICs, a 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is now necessary because ICs are 3D in their actual physical implementation. In this work, we study the EM reliability of the interconnects in ICs using a 3D finite element circuit model. A simplified circuit structure with only the intra-block interconnects is used as an example to show the construction of a 3D finite element model from its 2D IC layout. This modeling method is then used in the analysis of a realistic circuit structure with the inclusion of both intra-and inter-block interconnects. Transient electro-thermo-structural simulations are carried out using both Cadence (a circuit simulator) and ANSYS (a finite element tool). By limiting our study only to EM failure, the current density, temperature and thermo-mechanical stress II distributions of the interconnects are computed by considering the heat transfer and Joule heating, and these values are used to compute the atomic flux divergences

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“…6). We assume that the zone of maximal tensile stress leading to the void nucleation is right under the TSV, since the migration of incoming Cu atoms in this zone is blocked due to the TiN diffusion barrier whereas the atoms leaving the zone are driven by the electron flow, as explained by [13].…”

Section: Failure Analysismentioning

confidence: 99%

Electromigration behavior of 3D-IC TSV interconnects

Frank

Moreau

Chappaz

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances. Introduction3D integrated circuits based on TSV interconnects have become realistic approaches, increasing performances thanks to higher bandwidth [1, 2]. Regarding recent advances in TSV processes maturity, reliability investigation becomes critical to maximize performances, and especially to enable high current demands through the stacked package. Maximal direct current is given by the ageing of metallization under électromigration (EM) phenomenon, which is the movement of metal atoms, in response to current density. At interfaces of atoms flux divergences, EM leads to latencies accumulation and therefore to open circuit failure. Recent papers studied EM concerns at TSV interfaces, through simulation [3 -5], and also through first experimental approaches [6 -8].

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The effect of a width transition on the electromigration reliability of Cu interconnects

Cited by 17 publications

References 8 publications

Resistance increase due to electromigration induced depletion under TSV

Resistance increase due to electromigration induced depletion under TSV

3D electromigration modeling at the circuit layout level

Electromigration behavior of 3D-IC TSV interconnects

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