The Dragon Computer System

McCreight, Edward M.

doi:10.1007/978-94-009-5143-3_3

Cited by 28 publications

(22 citation statements)

References 5 publications

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“…In write-invalidate schemes [21,29,39], a write to a cached line results in invalidating copies of this line present in other caches. In write update schemes [36,49], a write to a cached line results in updating copies of this line present in other caches.…”

Section: Cache Coherence Protocolsmentioning

confidence: 99%

Cache-Based Synchronization in Shared Memory Multiprocessors

Ramachandran

Lee

1996

Journal of Parallel and Distributed Computing

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Section: Cache Coherence Protocolsmentioning

confidence: 99%

Cache-Based Synchronization in Shared Memory Multiprocessors

Ramachandran

Lee

1996

Journal of Parallel and Distributed Computing

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“…The "Dragon Protocol" is that used in the Dragon Processor at Xerox PARC, and is defined in [McCr84] and [Arch85]; we rely heavily on the latter due to the vagueness of the definition in the first paper• The Dragon protocol is implementable almost • exactly using the Futurebus features. The one exception is that when a broadcast write is done on the Futurebus, it affects all caches holding the line and also main memory.…”

Section: Dragon Protocolmentioning

confidence: 99%

A class of compatible cache consistency protocols and their support by the IEEE futurebus

Sweazey

Smith

1986

SIGARCH Comput. Archit. News

183

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Standardization of a high performance blackplane bus, so that it can accommodate boards developed by different vendors, implies the need for a standardized cache consistency protocol. In this paper we define a class of compatible consistency protocols supported by the current IEEE Futurebus design. We refer to this class as the MOESI class of protocols; the term "MOESI" is derived from the names of the states. This class of protocols has the property that any system component can select (dynamically) any action permitted by any protocol in the class, and be assured that consistency is maintained throughout the system. Included in this class are actions suitable for copyback caches, write through caches and non-caching processors. We show that the Berkeley protocol and the Dragon protocol fall within this class, and can be extended to be compatible with other members of the class. The Illinois, Firefly and Write-Once protocols can be adapted to be compatible with this class; the facilities of the Futurebus currently do not support those protocols without adaptation. We discuss very briefly performance choices among protocols, and also other issues relating to a standard bus consistency protocol.A thought: ",4 foolish consistency is the hobgoblin of little minds, adored by little statesmen and philosophers and devines." [Emer41]

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“…Few cache-coherent multiprocessors have incorporated the writeupdate protocol [43], despite significant early research. This is because few data items are write-shared by many threads of a typical parallel application at once.…”

Section: H Write Updatementioning

confidence: 99%

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading

Porter

Choi

Tullsen

2009

2009 18th International Conference on Parallel Architectures and Compilation Techniques

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Abstract-This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithreading. In particular, it explores the path from eager conflict detection HTM to full support of efficient speculative multithreading, focusing on the case where frequent memory dependencies exist between speculative threads. The result is a unified memory architecture capable of effective support for transactional parallel workloads and efficient speculative multithreading.

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The Dragon Computer System

Cited by 28 publications

References 5 publications

Cache-Based Synchronization in Shared Memory Multiprocessors

Cache-Based Synchronization in Shared Memory Multiprocessors

A class of compatible cache consistency protocols and their support by the IEEE futurebus

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading

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