The dielectric material dependence of stress and stress relaxation on the mechanism of stress-voiding of CU interconnects

Paik, Jong-Min; Jung, Jung-Kyu; Joo, Young‐Chang

doi:10.1109/relphy.2005.1493084

Cited by 5 publications

(6 citation statements)

References 16 publications

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“…Using the material thermo-mechanical properties, boundary conditions, stress free and stress temperatures provided in his paper, the thermal stress simulation is repeated using our model. well with the experimentally XRD measured stress [34].…”

Section: Physical Analysis Methodssupporting

confidence: 86%

“…The thermo-mechanical properties of the materials employed in the simulation are summarized in Table 3.3 as per the literature [86][87][88][89][90]. The stress simulation model developed in this work was verified using the stress simulation and experimental stress measurement data reported by Paik et al [34]. Using the material thermo-mechanical properties, boundary conditions, stress free and stress temperatures provided in his paper, the thermal stress simulation is repeated using our model.…”

Section: Physical Analysis Methodsmentioning

confidence: 99%

“…3.3). This finding is attributed to an increase in Ph.D. Thesis Chapter 4: Stress-induced Voiding in Cu Interconnects the in-plane stress components resulting from greater substrate constraint [22,34] and a larger amount of vacancies available in the wider M1 leads [10,13,14,17,18,22]. Interestingly, the SM reliability showed no significant difference for both Via chain structures I and II at the centre of the wafer where the diffusion barrier layer coverage at the via bottom sidewall was better.…”

Section: Stress Distribution Beneath Gouging Viamentioning

confidence: 99%

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Stress migration study of Cu/Low-k interconnect system

Lim¹

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The demand for high performance, high packing density and low power dissipation integrated circuits (IC) has caused downward scaling of feature sizes in very large-scale integration (VLSI) fabrication. However with the scaling of interconnect feature size; the interconnect delay, which is one of the key factors determining the overall performance of devices is severely penalized [1]. Therefore copper (Cu), which is well known for its lower resistivity and excellent resistance to electromigration (EM) and stress-induced voiding as compared to aluminum (Al) and its alloy, was introduced as the material for nanoscale interconnects [2-9]. However, when the efforts to develop an effective Cu etch process failed, dual damascene which is an elegant technique of inlaying metal for interconnects throughout the back-end-of-line (BEOL) becomes the preferred choice. Even though Cu dual damascene has already been proven to be process-friendly and costs effective, its reliability robustness is strongly process and structural dependent. Starting from 0.13 µm process, yield and reliability have become critical issues for the integration of Cu and low-k dielectrics. Poor yield is observed at wafer sort and even for those apparent good chips; the failure rates are unacceptable during accelerated life testing. Physical analysis has shown the formation of stress-induced voids to be either within or beneath vias [10-35]. As such, understanding on the phenomena of stress-induced voiding in Cu interconnects must be established so as to resolve these issues.

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Section: Physical Analysis Methodssupporting

confidence: 86%

Section: Physical Analysis Methodsmentioning

confidence: 99%

Section: Stress Distribution Beneath Gouging Viamentioning

confidence: 99%

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Stress migration study of Cu/Low-k interconnect system

Lim¹

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“…The tensile stress causes poor adhesion at the interface and electromigration is also strongly affected by the interaction of atomic fluxes when electrons flow from the high-resistance region to the lowresistance region under tensile stress, which means that the tensile stress pulls the metal films from the Si layer and forms voids, as seen between the Cu=TaN and Si layers, whereas the compressive stress pushes the metal films into the Si layer and provides a better interface. 28,31,35,36) Therefore, it is concluded that the stable contact resistance, low failure rate, and absence of voids in the Cu=WCN structures are due to the fact that the atomic flux divergence is obviously reduced by the stress evolution from tensile to compressive and the low contact resistance as well as the suppression of Cu diffusion at elevated temperatures. 38) Fig.…”

Section: Resultsmentioning

confidence: 99%

“…Mechanical hardness and adhesion were investigated by chemomechanical polishing (CMP) since the mechanical strength, surface energy, and thermal stability of the Cu=diffusion barrier=ILD=Si structure were closely related to the damascene process and adhesion of Cu. 27,28)…”

Section: Experimental Methodsmentioning

confidence: 99%

Performance of WCN diffusion barrier for Cu multilevel interconnects

Lee

Kim

2018

Jpn. J. Appl. Phys.

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The electrical and thermal properties of a WCN diffusion barrier have been studied for Cu multilevel interconnects. The WCN has been prepared using an atomic layer deposition system with WF 6 -CH 4 -NH 3 -H 2 gases and has a very low resistivity of 100 µΩ cm and 96.9% step coverage on the high-aspect-ratio vias. The thermally stable WCN maintains an amorphous state at 800 °C and Cu/WCN contact resistance remains within a 10% deviation from the initial value after 700 °C. The mean time to failure suggests that the Cu/WCN interconnects have a longer lifetime than Cu/TaN and Cu/WN interconnects because WCN prevents Cu migration owing to the stress evolution from tensile to compressive.

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Reliability Physics and Engineering

McPherson¹

2010

145

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The dielectric material dependence of stress and stress relaxation on the mechanism of stress-voiding of CU interconnects

Cited by 5 publications

References 16 publications

Stress migration study of Cu/Low-k interconnect system

Stress migration study of Cu/Low-k interconnect system

Performance of WCN diffusion barrier for Cu multilevel interconnects

Reliability Physics and Engineering

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