The Deterioration Phenomenon of Amorphous InSnZnO Transistors Derived from the Process of Annealing

Abstract

Thin-film transistors (TFTs) with transparent amorphous indium-tin-zinc-oxide (a-ITZO) channel were fabricated. The field effect mobility (μ) of the a-ITZO TFT was more than 15.0 cm 2 V −1 s −1 , which is higher than the generally reported value of amorphous indium-gallium-zinc-oxide (a-IGZO) TFT. However, μ deteriorated with a decreasing channel length of the a-ITZO TFT due to the annealing process after patterning of the ITZO. We studied the effects of the annealing process on the contact resistance between the a-ITZO film and the source/drain electrodes. A transmission line method (TLM) chart indicated that the parasitic resistances between the source/drain electrode and the back-channel region of the a-ITZO was 2 × 10 4 .Amorphous silicon thin-film transistors (a-Si:H TFTs) are widely used for active-matrix liquid crystal displays. However, a performance limit remains because the mobility of a-Si:H TFTs is at most 0.5 cm 2 V −1 s −1 , which is not enough to drive the next generation of flat panel displays. Therefore transparent amorphous oxide semiconductors (TAOS), whose mobility (μ) is over 10 times higher than the a-Si:H TFT, are considered prime candidates for practical use.In fact, several TAOS materials like zinc oxide, 1,2 indium-galliumzinc-oxide (a-IGZO), 3,4 zinc-tin oxide 5,6 and zinc-indium-oxide 7,8 have been studied for use in TFTs. In particular, a-IGZO is the most promising material and has been widely researched. Among the TAOS, we have also reported on amorphous indium-tin-zinc-oxide (a-ITZO) 9 as satisfying the demand for a higher μ TFT. This material is not only useful for high resolution displays, but also for driver circuits, memory devices and charge coupled devices. Since such applications require a shorter channel length to enhance their electrical properties, the contact resistivity between the back-channel of the a-ITZO and source/drain electrodes would be significant. 10 As for TFT fabrication, an annealing process is essential to stabilize the oxygen vacancies of the a-ITZO channel. However, the effect of the timing of the annealing process during the TFT fabrication on the contact resistivity is not yet clear. Due to the above reason, we fabricated two kinds of a-ITZO TFTs, with and without the annealing process, after patterning the ITZO channel, and compared their performance by measuring the contact resistance between the ITZO channel and source/drain electrodes. Experimental ProcedureTFT fabrication.-The 50-nm-thick a-ITZO films were deposited on a non-alkaline glass substrate by the RF magnetron sputtering of an ITZO ceramic target. Each concentration of In, Sn, Zn is under 50%. The deposition was performed at 150 • C in a mixed gas of Ar and O 2 at a deposition pressure of 1 Pa. The RF sputtering power was maintained at 100 W. The bottom-gate and etch-stopper type a-ITZO TFT was fabricated as follows. A 50-nm-thick Cr gate electrode was formed on a glass substrate. A 150-nm-thick SiOx film was deposited by plasma-enhanced chemical vapor deposition (PECVD) as a gate insulato...

Self-Aligned Amorphous Indium-Tin-Zinc-Oxide Thin Film Transistors on Polyimide Foil

“…In literature, XPS analysis showed that the annealed a-ITZO film has a lower amount of oxygen vacancy. 21 In contrary, for similar type of material (a-IGZO) based TFTs, it is reported that the improved electrical properties at higher anneal temperature suggest a decrease in the density of trap states localized below the conduction band. 3 Overall, we concluded that the a-ITZO film thickness of 8 nm with 30% O 2 content can be considered optimal for further integration.…”

A cost‐effective fluorination method for enhancing the performance of metal oxide thin‐film transistors

“…Compared to Device F1, Device F0 (Figure 4B) shows no hysteresis, a comparable V th and SS of −0.8 V and 81.6 mV/decade, a higher on‐off ratio of 1.5 × 10 10 , and improved saturation mobility (μ sat ) of 22.3 cm 2 /Vs. According to Tomai et al, 11 the annealing process before the ESL deposition may result in the generation of a depletion layer under the S/D electrodes and hence the increase of S/D contact resistance. Therefore, the increase of on‐off ratio and mobility in Device F0 can be plausibly explained.…”

8‐1: Distinguished Paper: A Cost‐Effective Fluorination Method for Enhancing the Performance of Metal Oxide Thin‐Film Transistors Using a Fluorinated Planarization Layer

“…3(a) shows the influence of the PLN process on the transfer curves of Device F1. With the cured F-PI layer, the device exhibits improved electrical characteristics with a positive shift of threshold voltage (Vth) from -3.3 V to -0.7 V, a decrease of subthreshold swing (SS) from 130.2 mV/decade to 80.8 mV/decade, and a rise of on-off ratio from 1.2×10 8 to 4.1×10 9 . The clockwise hysteresis phenomenon observed before the PLN process almost disappears.…”

“…Compared to Device F1, Device F0 shows no hysteresis and has a comparable Vth and SS of -0.8 V and 81.6 mV/decade, respectively. Probably due to the elimination of the additional annealing processes [9], the device owns relatively better S/D contacts with no current crowding effect in its output curves (Fig. 3(c)), leading to a higher on-off ratio of 1.5×10 10 and a boosted saturation mobility (µsat) of 22.3 cm 2 /Vs.…”