The Design of Way-Prediction Scheme in Set-Associative Cache for Energy Efficient Embedded System

Tseng, Chia-Ying; Chen, Hsin-Chu

doi:10.1109/cmc.2009.306

Cited by 5 publications

(3 citation statements)

References 7 publications

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“…There are two means to further improve the performance of Way-Predicting cache, that's to say, increasing the PHR or reducing the prediction-miss penalties. C. Tseng [6] adopted the MPLRU (Modified Pseudo Least Recently Used) replacement algorithm in Way-Predicting cache to augment the PHR and thus save energy consumption. Valid bits [7] are used in way-predicting caches with sub-block replacement policy, to pre-eliminate those hopeless sub-arrays and thus reduce average energy dissipation.…”

Section: Previous Researchmentioning

confidence: 99%

A Low Power Way-Predicting D-Cache with Partial Tag Comparison Filter

Cao

Zhang

2014

AMR

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This paper proposes a way-predicting algorithm which is specially equipped with a Partial Tag Comparison Filter (PTCF) to reduce the energy consumption in high associative D-caches. Conventional way-predicting algorithm achieves good performance and energy efficiency on I-cache which usually can guarantee the high prediction accuracy. However, the D-cache usually cannot reach such high prediction accuracy; therefore it suffers unavoidably from severe prediction inaccuracy penalties. The introduced PTCF aims at reducing energy penalties in case of prediction-miss and thus brings improvement in energy efficiency. The experiments show that the new D-cache reduces energy consumption by about 20%~60% without any latency degradation compared to conventional way-predicting D-cache.

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Section: Previous Researchmentioning

confidence: 99%

A Low Power Way-Predicting D-Cache with Partial Tag Comparison Filter

Cao

Zhang

2014

AMR

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“…It can also identify dead blocks with 96% accuracy leading to an average L1 improvement of 9% and L2 improvement of 10%. Tseng et al (2009) proposed a method to improve the problems of spatial and temporal locality by using a 2-bit counter to store the most recently used (MRU) information and Modified Pseudo LRU replacement algorithm (MPLRU): 1) To implement MRU, each cache set needs to have 2 bits of index to save the MRU status; and 2) To conduct MPLRU replacement policy, 3 bits are required to hold history information per block for 4-way way-prediction cache. Another method to fix the problems of locality is the use of Dynamic Time Tuning proposed by Zhang et al (2009).…”

Section: Related Workmentioning

confidence: 99%

A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

Chu¹,

Calagos²

2013

International Journal of Embedded and Real-Time Communication Systems

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This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP (energy delay product) up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.

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“…Microarchitectural techniques for saving energy in specific components e.g. main memory ( [82][83][84]), cache [6,16,35,[85][86][87][88][89][90][91][92][93][94][95][96][97][98][99][100][101][102][103], scratchpad memory [104], TLB [105] or making other changes to memory hierarchy e.g. adding extra components [106,107].…”

Section: Overviewmentioning

confidence: 99%

A survey of techniques for improving energy efficiency in embedded computing systems

Mittal¹

2014

IJCAET

133

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Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow.

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The Design of Way-Prediction Scheme in Set-Associative Cache for Energy Efficient Embedded System

Cited by 5 publications

References 7 publications

A Low Power Way-Predicting D-Cache with Partial Tag Comparison Filter

A Low Power Way-Predicting D-Cache with Partial Tag Comparison Filter

A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

A survey of techniques for improving energy efficiency in embedded computing systems

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