The Design Of UVM Verification Platform Based On Data Comparison

Zhou, Sheng; Geng, Shuqin; Peng, Xiaohong; Zhang, Mingming; Chu, Menghao; Li, PengKun; Zhu, Ronghao

doi:10.1145/3443467.3443908

Cited by 1 publication

(1 citation statement)

References 2 publications

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“…The module-level verification testbench should possess good reusability to enable coupling with the system and verification testbench. Zhou [4] proposed a UVM verification testbench that does not include a reference model component. This testbench focused on module-level verification, specifically targeting the main function of each module, without utilizing assertions and other verification methods.…”

Section: Introductionmentioning

confidence: 99%

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

Liu,

Xu,

Chen

et al. 2023

Electronics

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The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios.

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Section: Introductionmentioning

confidence: 99%