The design of mixed hardware/software systems

Adams, J.K.; Thomas, D.E.

doi:10.1109/dac.1996.545630

Cited by 24 publications

(20 citation statements)

References 11 publications

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“…The partitioning step is pushed back at the end of the lifecycle. We can thus settle that the choice of a specific lifecycle model which support a codesign approach [1] is required.…”

Section: The Approachmentioning

confidence: 99%

“…The second level relates to features for which there are several choices of implementation. Following criteria can be considered to be relevant for the agents according to our previous works in this field [5,4] and codesign works like [1]: the cost, the performance, the flexibility, the fault tolerance, the ergonomic contraints and the algorithmic complexity. At the Implementation Phase, each component is completely specified with a common graphic specification formalism for the hardware part and the software part.…”

Section: Implementation Stagementioning

confidence: 99%

See 1 more Smart Citation

About Some Specificities of Embedded Multiagent Systems Design

Samek

Šišlák

Volf

et al. 2007

2007 IEEE/WIC/ACM International Conference on Intelligent Agent Technology (IAT'07)

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“…The partitioning step is pushed back at the end of the lifecycle. We can thus settle that the choice of a specific lifecycle model which support a codesign approach [1] is required.…”

Section: The Approachmentioning

confidence: 99%

Section: Implementation Stagementioning

confidence: 99%

About Some Specificities of Embedded Multiagent Systems Design

Samek

Šišlák

Volf

et al. 2007

2007 IEEE/WIC/ACM International Conference on Intelligent Agent Technology (IAT'07)

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show abstract

“…An approach that generates new logic capabilities for a processor dynamically has been developed for an adaptive machine architecture in [12]. The work in [13] places ASIP synthesis in the context of hardware-software cosynthesis. It argues that, since the customized instructions added to an existing instruction set are implemented in hardware, whereas the original instructions are run on the basic processor core, ASIP synthesis is a variant of hardware-software partitioning.…”

Section: A Related Workmentioning

confidence: 99%

Custom-Instruction Synthesis for Extensible-Processor Platforms

Sun

Ravi²,

Raghunathan³

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Efficiency and flexibility are critical, but often conflicting, design goals in embedded system design. The recent emergence of extensible processors promises a favorable tradeoff between efficiency and flexibility, while keeping design turnaround times short. Current extensible processor design flows automate several tedious tasks, but typically require designers to manually select the parts of the program that are to be implemented as custom instructions. In this work, we describe an automatic methodology to select custom instructions to augment an extensible processor, in order to maximize its efficiency for a given application program. We demonstrate that the number of custom instruction candidates grows rapidly with program size, leading to a large design space, and that the quality (speedup) of custom instructions varies significantly across this space, motivating the need for the proposed flow. Our methodology features cost functions to guide the custom instruction selection process, as well as static and dynamic pruning techniques to eliminate inferior parts of the design space from consideration. Furthermore, we employ a two-stage process, wherein a limited number of promising instruction candidates are first short-listed using efficient selection criteria, and then evaluated in more detail through cycle-accurate instruction set simulation and synthesis of the corresponding hardware, to identify the custom instruction combinations that result in the highest program speedup or maximize speedup under a given area constraint. We have evaluated the proposed techniques using a state-of-the-art extensible processor platform, in the context of a commercial design flow. Experiments with several benchmark programs indicate that custom processors synthesized using automatic custom instruction selection can result in large improvements in performance (up to 5.4 , an average of 3.4 ), energy (up to 4.5 , an average of 3.2 ), and energy-delay products (up to 24.2 , an average of 12.6 ), while speeding up the design process significantly.

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“…The second level relates to features for which there are several choices of implementation. We present below, those which can be considered to be relevant for the agents according to previous works we have made in this field (Occello et al, 1998), (Jamont et al, 2002), (Luo et al, 2007) and codesigns work like (Adams & Thomas, 1996):…”

Section: Implementation Stagementioning

confidence: 99%