The Design of a 2D Graphics Accelerator for Embedded Systems

Abstract

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension

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Intelligent Monitoring System with Privacy Preservation Based on Edge AI

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ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator

“…Therefore, before designing a k-NN accelerator, it is necessary to review and optimize the structure of a k-NN accelerator suitable for a specific problem. It is similar to testing hardware logic in FPGA before application-specific integrated circuit (ASIC) [ 36 , 37 , 38 ]. Therefore, in order to overcome this problem, this study proposes an ASimOV framework that examines and optimizes various k-NN accelerators to generate HDL code that can be executed directly on the FPGA.…”