The Design of 3D‐Interface Architecture in an Ultralow‐Power, Electrospun Single‐Fiber Synaptic Transistor for Neuromorphic Computing

Abstract

Synaptic electronics is a new technology for developing functional electronic devices that can mimic the structure and functions of biological counterparts. It has broad application prospects in wearable computing chips, human–machine interfaces, and neuron prostheses. These types of applications require synaptic devices with ultralow energy consumption as the effective energy supply for wearable electronics, which is still very difficult. Here, artificial synapse emulation is demonstrated by solid‐ion gated organic field‐effect transistors (OFETs) with a 3D‐interface conducting channel for ultralow‐power synaptic simulation. The basic features of the artificial synapse, excitatory postsynaptic current (EPSC), paired‐pulse facilitation (PPF), and high‐pass filtering, are successfully realized. Furthermore, the single‐fiber based artificial synapse can be operated by an ultralow presynaptic spike down to −0.5 mV with an ultralow reading voltage at −0.1 mV due to the large contact surface between the ionic electrolyte and fiber‐like semiconducting channel. Therefore, the ultralow energy consumption at one spike of the artificial synapse can be realized as low as ≈3.9 fJ, which provides great potential in a low‐power integrated synaptic circuit.

Sub‐Femtojoule‐Energy‐Consumption Conformable Synaptic Transistors Based on Organic Single‐Crystalline Nanoribbons

“…Figure 1g displays the statistical results of low‐power synaptic transistors over the past five years. [ 18–26 ] Noteworthy, the E c of our device is at least an order of magnitude lower than that of all the reported nanowire‐based synaptic transistors (Table S2, Supporting Information). Compared to organic nanowire‐based synaptic transistors, the key reason is that they used polycrystalline nanowires as the active layer.…”

“…To enable these polycrystalline nanowire‐based devices to be functioned normally at a low voltage, ion‐gel dielectric has to be used in the previously reports. [ 18,19 ] Although the high‐ C i ionic‐gel dielectric is beneficial to the reduction of operating voltage, it inevitably leads to higher current (Table S3, Supporting Information). [ 37–40 ] Consequently, the E c of polycrystalline nanowire‐based device is usually higher than the femtojoule magnitude.…”

“…[ 1,2 ] They only consume ultralow energy (10 fJ one synaptic event) to achieve complex parallel operations, so that operating a huge neural network (≈10 15 synapses) only consumes extremely little energy, even lower than that of a household light bulb (≈20 W). Inspired by the biological synapses, the artificial synapses including two‐terminal synapses [ 3–17 ] and three‐terminal synaptic transistors [ 18–36 ] have arisen to simulate basic synaptic plasticity such as short‐term plasticity (STP), long‐term plasticity (LTP), paired‐pulse facilitation (PPF), and so on. However, current artificial synapses usually consume orders of magnitude more energy than biological synapses, which will inevitably cause tremendous energy consumption for simulating the brain‐like neuromorphic network.…”

“…Synaptic transistors based on 1D organic nanowires have shown great potentials in developing the low‐energy‐consumption artificial synapses, [ 18,19 ] which mainly originate from the following two reasons. On the one hand, transistor‐type synapses compared with two‐terminal counterparts can regulate external information through the third terminal (gate electrode), and learning and remembering are performed concurrently, closer the biological synaptic learning behaviors.…”

“…also prepared a poly(3,3′′′‐didodecyl quarter thiophene)/poly(ethylene oxide) (PQT‐12/PEO) synaptic transistor based on the ionic gel dielectric layer with the energy consumption only 3.9 fJ. [ 19 ] Despite these results have shown a low energy consumption, it should be noted that they both applied polycrystalline nanowires as the active layer, so the ionic‐gel dielectric had to be utilized for enabling the device to operate normally under a low voltage. Indeed, the ionic‐gel dielectric with a large gate insulator capacitance ( C i ) is feasible in reducing voltage but gives rise to higher current especially in low frequency, [ 37–40 ] hence energy consumption cannot be further optimized effectively.…”