The design, implementation and evaluation of SMART

Nieh, Jason; Lam, Monica S.

doi:10.1145/268998.266677

Cited by 171 publications

(98 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…SMART [67] is in this category: it supports a mixed programming model in which applications receiving proportional share scheduling can meet real-time requirements using the deadline-based time constraint abstraction. BVT [20] associates a warp value with each application; non-zero warp values allow a thread to build up credit while blocked, increasing the chances that it will be scheduled when it wakes up.…”

Section: Proportional Sharementioning

confidence: 99%

“…For example, SMART [67] supports the time constraint abstraction that allows an application to request a certain amount of CPU time before a deadline. If SMART informs an application that a time constraint is feasible, but the constraint later becomes infeasible (for example, due to the awakening of a higher-priority task), SMART may notify the application of the infeasible constraint, potentially allowing the application to avoid performing a useless computation.…”

Section: Supported and Unsupported Classes Of Schedulersmentioning

confidence: 99%

“…And yet they are still useful-millions of people run multimedia applications on these operating systems using the techniques described in Section 3.4. Other classes of schedulers that provide no guarantees to applications include feedback-and progress-based schedulers, hybrid real-time schedulers such as SMART [67], and modified proportional share schedulers like BVT [20] and the modified Lottery scheduler developed by Petrou et al [71]. The common theme across all of these schedulers is that they attempt to provide high value across the set of all running applications by dynamically allocating CPU time to where it is believed to be needed most.…”

Section: Applicability Of Guaranteesmentioning

confidence: 99%

“…Furthermore, the scheduler, in conjunction with applications, must meet user expectations and provide understandable behavior in the face of sets of applications that demand resources exceeding the capacity of the system. For example, SMART [67] and Rialto [40] both offer deadline-based scheduling to applications in the form of time constraints. To use a time constraint, an application requests an amount of CPU time before a deadline (for example, 20 ms of processing during the next 100 ms); the scheduler then notifies the application that the constraint is either accepted or rejected.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Using Hierarchical Scheduling to Support Soft Real-Time Applications in General-Purpose Operating Systems

Stankovic¹,

Regehr²

View full text Add to dashboard Cite

The CPU schedulers in general-purpose operating systems are designed to provide fast response time for interactive applications and high throughput for batch applications. The heuristics used to achieve these goals do not lend themselves to scheduling real-time applications, nor do they meet other scheduling requirements such as coordinating scheduling across several processors or machines, or enforcing isolation between applications, users, and administrative domains. Extending the scheduling subsystems of general-purpose operating systems in an ad hoc manner is time consuming and requires considerable expertise as well as source code to the operating system. Furthermore, once extended, the new scheduler may be as inflexible as the original.The thesis of this dissertation is that extending a general-purpose operating system with a general, heterogeneous scheduling hierarchy is feasible and useful. A hierarchy of schedulers generalizes the role of CPU schedulers by allowing them to schedule other schedulers in addition to scheduling threads. A general, heterogeneous scheduling hierarchy is one that allows arbitrary (or nearly arbitrary) scheduling algorithms throughout the hierarchy. In contrast, most of the previous work on hierarchical scheduling has imposed restrictions on the schedulers used in part or all of the hierarchy.This dissertation describes the Hierarchical Loadable Scheduler (HLS) architecture, which permits schedulers to be dynamically composed in the kernel of a general-purpose operating system. The most important characteristics of HLS, and the ones that distinguish it from previous work, are that it has demonstrated that a hierarchy of nearly arbitrary schedulers can be efficiently implemented in a general-purpose operating system, and that the behavior of a hierarchy of soft real-time schedulers can be reasoned about in order to provide guaranteed scheduling behavior to application threads. The flexibility afforded by HLS permits scheduling behavior to be tailored to meet complex requirements without encumbering users who have modest requirements with the performance and administrative costs of a complex scheduler.Contributions of this dissertation include the following.(1) The design, prototype implementation, and performance evaluation of HLS in Windows 2000. (2) A system of guarantees for scheduler composition that permits reasoning about the scheduling behavior of a hierarchy of soft real-time schedulers. Guarantees assure users that application requirements can be met throughout the lifetime of the application, and also provide application developers with a model of CPU allocation to which they can program. (3) The design, implementation, and evaluation of two augmented CPU reservation schedulers, which provide increase scheduling predictability when low-level operating system activity steals time from applications. iv AcknowledgmentsFirst of all, many thanks to my advisor Jack Stankovic for being supportive of me and my work, for giving me enough rope but not too much, for pushi...

show abstract

Section: Proportional Sharementioning

confidence: 99%

Section: Supported and Unsupported Classes Of Schedulersmentioning

confidence: 99%

Section: Applicability Of Guaranteesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Using Hierarchical Scheduling to Support Soft Real-Time Applications in General-Purpose Operating Systems

Stankovic¹,

Regehr²

View full text Add to dashboard Cite

show abstract

“…The problem is shown in figure 5.9, with the black and blue paths representing the case of fixed resources, where the problem is rather trivial: each cycle, simply select a free resource capable of executing each instruction until there are no idle resources or no instructions left, the number of total instructions sent to functional units being bound by the issue width. This is the job done by the scheduler in a superscalar processor [28,63]. The reservation stations simplify this work by maintaining queues in front of each functional unit or type of functional unit.…”

Section: Problem Definitionmentioning

confidence: 99%

Adding limited reconfigurability to superscalar processors

Epalza

Ienne²,

Mlynek

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.

View full text Add to dashboard Cite

For the last thirty years, electronics, at first built with discrete components, and then as Integrated Circuits (IC), have brought diverse and lasting improvements to our quality of life. Examples might include digital calculators, automotive and airplane control assistance, almost all electrical household appliances, and the almost ubiquitous Personal Computer. ApplicationSpecific Integrated Circuits (ASICs) were traditionally used for their high performance and low manufacturing cost, and were designed specifically for a single application with large volumes. But as lower product lifetimes and the pressures of fast marketing increased, ASICs' high design cost pushed for their replacement by Microprocessors. These processors, capable of implementing any functionality through a change in software, are thus often called General Purpose Processors.General purpose processors are used for everyday computing tasks, and found in all personal computers. They are also often used as building blocks for scientific supercomputers. Superscalar processors such as these require ever more processing power to run complex simulations, video games or versatile telecoms services. In the case of embedded applications, e.g. for portable devices, both performance and power consumption must be taken into account.In a bid to adapt a processor to some extent to select applications, fully reconfigurable logic can greatly improve the performance of a processor, since it is shaped for the best possible execution with the available resources. However, as reconfigurable logic is far slower than custom logic, this gain is possible only for some specific applications with large parallelism, after a detailed study of the algorithm. Even though this process can be automated, it still requires large computing resources, and cannot be performed at run time.To reduce the loss in speed compared to custom logic, it is possible to limit the reconfigurability to increase the breadth of applications where performance can be improved. However, as the application space increases, a careful analysis and design of the reconfigurability is required to minimize the speed loss, notably when dynamic reconfiguration is considered.iii iv As a case study, we analyze the feasibility of adding limited reconfigurability to the Floating Point Units (FPUs) of a general purpose processor. These rather large units execute all floating point operations, and may also be used for integer multiplication. If an application contains few or infrequent instructions that must be executed by the FPU, this idle hardware only increases power consumption without enhancing performance. This is often the case in non-scientific applications and even many recent and detailed video games which make heavy use of hardware display accelerators for 3D graphics.In a fast multiplier such as can be found in the FPU of a high performance processor, the logic to perform multiplication is a large tree of compressors to add all the partial products together. It is possible to add logic to a...

show abstract

OSfor Graphics and Multimedia

Yau

2009

Wiley Encyclopedia of Computer Science and Engineering

View full text Add to dashboard Cite

Multimedia and graphics data including video, audio, and realistic animations, are entertaining, informative, and intuitive. The information is continuously updated, in which the timing of the data is part of their semantics, and must be maintained both within a data stream and between related data streams. Operating system support for the soft real-time needs of multimedia applications is crucial and challenging. In this article, we discuss OS support for multimedia quality of service in a general-purpose and multi-user computing environment. We address the issues of (1) resource abstraction and accounting, (2) resource scheduling, and (3) solutions to priority inversion problems arising out of interactions between OS components.

show abstract

The design, implementation and evaluation of SMART

Cited by 171 publications

References 17 publications

Using Hierarchical Scheduling to Support Soft Real-Time Applications in General-Purpose Operating Systems

Using Hierarchical Scheduling to Support Soft Real-Time Applications in General-Purpose Operating Systems

Adding limited reconfigurability to superscalar processors

OSfor Graphics and Multimedia

Contact Info

Product

Resources

About