The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing

Yeh, Chung-Huang; Chen, Jwu E.

doi:10.1109/itc-asia51099.2020.00027

Cited by 7 publications

(12 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Due to uncertainty factors in the manufacturing environment (mask error, etching and chemical concentration errors) after manufacturing, we assume the chip delay time of a device under test (DUT) is normal. Therefore, chip(x) = N(x; µ M , σ M ) with mean µ M and standard deviation σ M [2][3][4]:…”

Section: Calculating Manufacturing Yield (Y M ) and Predicting Manufacturing Progress Variationmentioning

confidence: 99%

“…From this third test, only the FPP parts (those previously failed chips that passed the second and third rounds) are reserved. We call this method "unbalance testing," a triple-test (M 3+ Un ) scheme [1][2][3][4], and the (M 3+ Un ) formula is defined as…”

Section: New Unbalanced Testing Schemementioning

confidence: 99%

“…Thus, estimating future product distribution trends using current manufacturing capability and existing product electrical characteristic parameters and conditions is a critical topic. In this study, we used a digital integrated-circuit (DITM) test model [1][2][3][4] using the existing manufacturing technology along with the electrical performance of existing products to estimate the future distribution trend of IC products. According to an update to the International Technology Roadmap for Semiconductors (ITRS), manufacturing speed and testing progress will significantly change in the future, with product manufacturability increasing by 30% annually and testing abilities rising by 12% annually [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Unbalanced-Tests to the Improvement of Yield and Quality

Yeh

Chen

2021

Electronics

Self Cite

View full text Add to dashboard Cite

An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.

show abstract

Section: Calculating Manufacturing Yield (Y M ) and Predicting Manufacturing Progress Variationmentioning

confidence: 99%

Section: New Unbalanced Testing Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Unbalanced-Tests to the Improvement of Yield and Quality

Yeh

Chen

2021

Electronics

Self Cite

View full text Add to dashboard Cite

show abstract

“…Coupled with the high chip demand for new energy vehicles, the global chip shortage has caused a supply crisis in the global semiconductor industry chain (global chip shortage). Three effective retesting schemes [20][21][22] are proposed to improve the test quality (Y q ) and yield (Y t ) to solve the aforementioned problem. The goal of zero defects is achieved through the retesting of the changes in the test guardband (TGB).…”

Section: Introductionmentioning

confidence: 99%

Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband

Yeh,

Chen

2023

Eng

Self Cite

View full text Add to dashboard Cite

The digital integrated circuit (IC) testing model module is applied in this study to simulate the fabrication and testing of integrated circuits. The yield and quality of ICs are analyzed by assuming that the wafer devices under test conditions are normal probability distributions. The difficulties of testing and verification become increasingly great as the design function of the chip becomes remarkably complex. Conversely, the automotive industry chip supply chain has been substantially affected since the COVID-19 outbreak. The shortage of chips in the auto-market has always existed; therefore, increasing available chips under a limited production capacity has become a top priority. Therefore, this study applies the digital integrated circuit testing model (DITM) and proposes a retest plan. This method does not require considerable time to collect large wafer data, nor does it require additional hardware equipment. Furthermore, the required test quality parameters are set, and the test is repeated on the device by adjusting the test guardband (TGB). Moreover, three retesting schemes are proposed to improve the IC test quality (Yq) and test yield (Yt) to meet the requirements of consumers for product quality. A set of 2021 IEEE International Roadmap for Devices and Systems (IRDS) parameters is used to demonstrate the three proposed retesting schemes. The simulation results from the 2021 IRDS data prove that the retest method can effectively improve the test yield (Yt). A comparison of the estimated results of the three retest methods shows that using the repeat test method can maximize the test yield without sacrificing the test quality (Yq). By contrast, repeat testing can indeed improve the test yield (Yt) by 14% or more. Moreover, the increase in sellable ICs not only increases additional earnings for corporations, but also alleviates the current global shortage of automotive ICs.

show abstract

“…Therefore, we propose repeating the test method (three-repetition tests scheme, TRTS) in pursuit of high-quality production methods. Using the ATE (automated test equipment) with poor performance, changing the test method, and moving the test guardband (TGB) [15][16][17][18][19][20][21], repeatedly find a truly zero-defect and reliable product to ensure that the chip can function normally and consistently. We referred to the IRDS (International Roadmap for Devices and Systems 2021) data [22] sheet to estimate the future test yield distribution.…”

Section: Introductionmentioning

confidence: 99%

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect

Yeh

Chen

2022

Sensors

View full text Add to dashboard Cite

In this research, the normal distribution is assumed to be the product characteristic, and the DITM (Digital Integrated Circuit Test Model) model is used to evaluate the integrated circuits (IC) test yield and test quality. Testing technology lags far behind manufacturing technology due to the different rates of development of the two technologies. As a result, quality control will pose significant challenges in pursuing high-quality near-zero defect products (automotive and biomedical electronics and avionics, etc.). In order to ensure product quality, we propose an effective repeated testing method (three-repetition tests scheme, TRTS), which utilizes the move test guardband (TGB) to improve the test yield and test quality. Based on the data in the International Roadmap for Devices and Systems table in 2021, the DITM model is used to estimate the future trend of semiconductor chip test yield, and the retest method (TRTS) is applied improve the test results. The method of repeated testing can increase the test yield and increase the shipment of semiconductor products. By estimating the test cost and profit, the method of repeated testing can obtain chips with near-zero defects with more corporate profits through increased product shipments.

show abstract

The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing

Cited by 7 publications

References 9 publications

Unbalanced-Tests to the Improvement of Yield and Quality

Unbalanced-Tests to the Improvement of Yield and Quality

Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect

Contact Info

Product

Resources

About