2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) 2020
DOI: 10.1109/bcicts48439.2020.9392956
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The DARPA Millimeter Wave Digital Arrays (MIDAS) Program

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Cited by 9 publications
(7 citation statements)
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“…The capability of the proposed architecture to process in parallel multiple beams at the transmitter and at the receiver greatly reduces the issues related to network discovery, cell search, and initial access [59] which become more and more problematic as narrower beams are formed by the BTS and for scenarios where node location is not known a priori [28]. Recent simulation-based results confirming initial access latency reductions when the BTS supports multiple beams at the transmit side were recently reported in [48].…”
Section: Multi-band Multi-beam Transmit Architecturementioning
confidence: 87%
See 3 more Smart Citations
“…The capability of the proposed architecture to process in parallel multiple beams at the transmitter and at the receiver greatly reduces the issues related to network discovery, cell search, and initial access [59] which become more and more problematic as narrower beams are formed by the BTS and for scenarios where node location is not known a priori [28]. Recent simulation-based results confirming initial access latency reductions when the BTS supports multiple beams at the transmit side were recently reported in [48].…”
Section: Multi-band Multi-beam Transmit Architecturementioning
confidence: 87%
“…This beamforming and 0.6-2.5 GHz for analog beamforming 2 . For comparison, the BBP goal set by DARPA for Phase 2 of its MIDAS program is at least 3.2 GHz using digital beamforming [28]. With 2.4 GHz of IF bandwidth in each beam, and 15 beams formed simultaneously and continuously, the system proposed in this paper has a nominal BBP of 36 GHz which is an order of magnitude higher than what is considered achievable with all electronic implementations.…”
Section: B Receiver Architecturementioning
confidence: 98%
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“…To enhance performance and reduce size, weight, and power consumption, multiple types of active and passive devices, each serving different functions, need to be integrated in an assembly or tile. In recent years, wafer-level three-dimensional integration technology has emerged as an attractive method for achieving higher performance and higher density of radio frequency (RF) components [1][2][3]. Concurrently, several vertical interconnect technologies for RF chips have undergone continuous evolution [4].…”
Section: Introductionmentioning
confidence: 99%