The CompSOC design flow for virtual execution platforms

Abstract

Designing a SoC for applications with mixed time-criticality is a complex and time-consuming task. Even when SoCs are built from components with known real-time properties, they still have to be combined and configured correctly to assert that these properties hold for the complete system, which is non trivial. Furthermore, applications need to be mapped to the available hardware resources and correctly integrated with the SoC's software stack, such that the realtime requirements of the applications are guaranteed to be satisfied. However, as systems grow in complexity, the design and verification effort increases, which makes it difficult to satisfy the tight time-to-market constraint.Design tools are essential to speed up the development process and increase profit. This paper presents the design flow for the CompSOC FPGA platform: a template for SoCs with mixed time-criticality applications. This work outlines how the development time of such a platform instance is reduced by means of its comprehensive tool flow, that aids a system designer in creating hardware, the associated software stack, and application mapping.

Cloud-based Design and Virtual Prototyping Environment for Embedded Systems

“…It allows the user to start quickly with setting up new virtual platforms for a targeted hardware architecture and PAPER CLOUD-BASED DESIGN AND VIRTUAL PROTOTYPING ENVIRONMENT FOR EMBEDDED SYSTEMS performing simulations, without the need of a long training period. Besides the original focus of providing a webbased GUI for OVP, SimplifyDE is integrated in the hardware and software flow as shown in Figure 1, targeting the FlexTiles Development Platform [11] that is based on the CompSOC design flow [12] including support for the realtime operating system CoMik [13] and its communication services. Thus, SimplifyDE can generate and export XML-files which describe the hardware and are compatible to the hardware flow and can be used to synthesize an FPGA design directly (see (a) in Figure 1).…”

“…Thus, SimplifyDE can generate and export XML-files which describe the hardware and are compatible to the hardware flow and can be used to synthesize an FPGA design directly (see (a) in Figure 1). Furthermore, SimplifyDE is integrated in the software flow [12] developed for the operating system to generate code templates containing all management code and hardware abstraction layers (block (b) in Figure 1). This hides the complexity of this code from the user who only needs to insert own functions as described later in section B of this chapter.…”

“…The targeted architecture of the multi-processor layer of the hardware is depicted in Figure 5 and is an instance of the FlexTiles Development Platform [11] [12]. This design flow provides a tile based template for creating SoCs for running applications with mixed time-criticality.…”

Composable and Predictable Dynamic Loading for Time-Critical Partitioned Systems

“…Moreover, with best-effort loading, the loading time is not predictable. A design-flow to generate a multi-tile partitioned system prototyped on an FPGA is proposed in [8], where applications share resources composably, i.e. they do not affect each other even by a single cycle.…”

“…That is, dynamic loading should be composable. Composable dynamic loading for partitioned systems is challenging because a) the existing state-of-art partitioned systems [3,4,7,8] do not support dynamically creating and managing partitions at run-time and b) existing loading methods [9]- [12] do not provide timing isolation between the running applications and the loading process and vice versa.…”