The Cibola Flight Experiment

Quinn, Heather; Roussel-Dupré, D.; Caffrey, M.; Graham, Paul; Wirthlin, Michael; Morgan, Keith S.; Salazar, Anthony; Nelson, Tony; Howes, Will; Johnson, Eric K.; Johnson, Jon; Pratt, B.; Rollins, Nathan; Krone, J.

doi:10.1145/2629556

Cited by 24 publications

(14 citation statements)

References 21 publications

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“…The Cibola Flight Experiment (CFE) [8], developed by Los Alamos National Laboratory and launched in 2007, is one of the most relevant examples. Its goal was actually to evaluate the feasibility of using SRAM-based FPGAs for on-board processing.…”

Section: A Rad-hard Sram-based Fpgas In Space Missionsmentioning

confidence: 99%

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

et al. 2020

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This paper describes a reconfigurable architecture for an on-board processor to be used in space exploration critical systems. It relies on, a dynamically reconfigurable multi-accelerator hardware architecture that provides transparent reconfiguration and scalable performance, dependability, and power consumption, at run-time. The architecture is integrated under an RTEMS operating system, which manages reconfiguration and fault mitigation in a fully-compatible way with space requirements. In this work, the proposed processor is used to implement a vision-based navigation system, providing fully autonomous adaptation to different phases of a space mission timeline or events that the spacecraft may encounter during its lifespan. Results show that reconfigurability enables the practical usage of Commercial Off-The-Shelf (COTS) Multiprocessor Systems-on-Chips (MPSoCs) in real scenarios. INDEX TERMS Vision-based navigation, reconfigurable on-board processor, high performance embedded computing, real-time operating systems.

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Section: A Rad-hard Sram-based Fpgas In Space Missionsmentioning

confidence: 99%

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

et al. 2020

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“…Wirthlin in [4] summarized common design practices for high reliable FPGA systems including hardware redundancy, configuration scrubbing, error-correction coding, flip-flop mitigation, and system-level mitigation of FPGA single-event effects (SEEs). That work highlights the importance of combinations of hardware redundancy, especially Triple-Modular Redundancy (TMR), and configuration scrubbing as a recovering mechanism in systems being used in satellites [2]. Moreover, Abramovici et al proposed the idea of rotating functional units via PR for testing and repairing in [21].…”

Section: Designing For Reliabilitymentioning

confidence: 99%

“…Furthermore, there are strong needs to use FPGAs in other application domains such as in automotive, aerospace, defense, cyber-security and in hazardous environments (e.g., in space [2] or high-energy physics [3]) which often require secure and safety-critical system implementations. However, these applications are challenging to implement with FPGAs.…”

Section: Introductionmentioning

confidence: 99%

IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

Pham¹,

Horta²,

Koch³

et al. 2018

2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC)

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FPGA devices have been used widely in many industrial domains, but only limitedly in secure and safety-critical applications, which have special requirements for the physical implementation, such as module isolation. This is partly due to limited functionality available with current FPGA vendors' tools and flows. To extend FPGA's appearance in secure and safetycritical applications, we propose an alternative flow for isolation design called the Isolated Partial Reconfiguration Design Flow (IPRDF) in this paper. Systems designed by the proposed IPRDF are not only fully isolated but also support partial reconfiguration of insulated modules. This allows building secure and dependable systems that can use partial reconfiguration to mitigate from single-event upsets (SEUs) and that are more tolerant to aging and device imperfections. Further, this also allows information assurance applications to benefit from hardware module isolation and run-time reconfigurability. Case studies on isolated Triple Modular Redundancy (TMR) and single-chip cryptographic (SCC) designs are presented to demonstrate capabilities and advantages of the proposed IPRDF methodology.

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“…For example, in the Cibola Flight Experiment [23], the experiment's Virtex FPGAs experienced an average SEU rate of 3.51 SEUs/day compared to their scrubbing cycle of 180 ms. With this assumption, based on our definitions, the total number of possible faults (and errors) is equal to the total number of resources used by the solution. Due to the likely use of SRAM-based FPGAs, we assume that all faults persist until scrubbing removes the fault.…”

Section: International Journal Of Reconfigurable Computingmentioning

confidence: 99%

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.

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The Cibola Flight Experiment

Cited by 24 publications

References 21 publications

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation

IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

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