The cache complexity of multithreaded cache oblivious algorithms

Frigo, Matteo; Strumpen, Volker

doi:10.1145/1148109.1148157

Cited by 44 publications

(65 citation statements)

References 27 publications

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“…1 shows, for example, the memory hierarchy for the Xeon based Nehalem architecture, the current generation of desktop architecture from Intel. Correspondingly there has been significant recent work on parallel cache based locality [1,8,5,19,11,7,4,12,23,9,13]. The work has fallen into two main classes.…”

Section: Introductionmentioning

confidence: 99%

“…Dynamic parallelism can be further divided between approaches in which the user analyzes their algorithm in an abstract model that knows nothing about the scheduler and its interaction with the machine [1,8,19,11,9], and approaches in which the analysis requires an integrated analysis [7,12,13,15,14]. In the first class the scheduler is required to supply a general mapping from an abstract cost model to the particular machine models.…”

Section: Introductionmentioning

confidence: 99%

“…In the first class the scheduler is required to supply a general mapping from an abstract cost model to the particular machine models. A pair of common abstract measures are the number of misses given a sequential ordering of a parallel computation [1,8,19,9] and the depth of the computation. For example, one can show that any nested-parallel computation with depth D and sequential complexity Q 1 will have at most Q 1 + O(P DM/B) misses on a parallel machine with P processors, each with a private cache of size M and block size B, when using a work-stealing scheduler [1].…”

Section: Introductionmentioning

confidence: 99%

“…The existing approaches mentioned above, however, have some important limitations. They either apply to hierarchies of only private or only shared caches [1,8,19,15,9], require some strict balance criteria [7,14], or require a per algorithm analysis [13]. In this paper we present a model and corresponding scheduler that enables an analysis that is independent of the scheduler, allows for arbitrary imbalance among tasks, and works on hierarchies of shared and private caches (as in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Scheduling irregular parallel computations on hierarchical caches

Blelloch

Fineman

Gibbons

et al. 2011

Proceedings of the Twenty-Third Annual ACM Symposium on Parallelism in Algorithms and Architectures

102

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Making efficient use of cache hierarchies is essential for achieving good performance on multicore and other shared-memory parallel machines. Unfortunately, designing algorithms for complicated cache hierarchies can be difficult and tedious. To address this, recent work has developed high-level models that expose locality in a manner that is oblivious to particular cache or processor organizations, placing the burden of making effective use of a parallel machine on a runtime task scheduler rather than the algorithm designer/programmer. This paper continues this line of work by (i) developing a new model for parallel cache cost, (ii) developing a task scheduler for irregular tasks on cache hierarchies, and (iii) proving that the scheduler assigns tasks to processors in a work-efficient manner (including cache costs) relative to the model. As with many previous models, our model allows algorithms to be analyzed using a single level of cache with parameters M (cache size) and B (cache-line size), and algorithms can be written cache obliviously (with no choices made based on machine parameters). Unlike previous models, our cost Q α (n; M, B), for problem size n, captures costs due to work-space imbalance among tasks, and we prove a lower bound that shows that some sort of penalty is needed to achieve work efficiency. Nevertheless, for many algorithms, Q α () is asymptotically equal to the standard sequential cache cost Q().Our task scheduler is a specific "space-bounded scheduler," which assigns subtasks to caches based on their space usage. Our scheduler extends prior work by efficiently scheduling "irregular" computations with arbitrary work imbalance among parallel subtasks, reflected by the Q α () cost. Moreover, in addition to proving bounds on cache complexity, we also provide a bound on the total running time of an program execution using our scheduler. Specifically, our scheduler executes a program on a homogeneous h-level parallel memory hierarchy having p processors in time O (v h /p) h i=0 Q α (n; M i , B) · C i , where M i is the size of the level-i cache, B is the cache-line size, C i is the cost of level-i cache miss, and v h is an overhead defined in the paper. Ignoring the overhead v h , which may be small (or even constant) when certain side conditions hold, this bound is optimal whenever Q α () matches the sequential cache complexity-at every level of the hierarchy it is dividing the total cache cost by the total number of processors.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Scheduling irregular parallel computations on hierarchical caches

Blelloch

Fineman

Gibbons

et al. 2011

Proceedings of the Twenty-Third Annual ACM Symposium on Parallelism in Algorithms and Architectures

102

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“…Using results from [1,18] (e.g., Theorem 2 and equation (4) of [18]) one can show that I-GEP incurs O(…”

Section: B ) Cache Misses When Executing Multithreaded I-gep On a Macmentioning

confidence: 99%

The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation

Chowdhury

Ramachandran

2010

Theory Comput Syst

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We consider triply-nested loops of the type that occur in the standard Gaussian elimination algorithm, which we denote by GEP (or the Gaussian Elimination Paradigm). We present two related cache-oblivious methods I-GEP and C-GEP, both of which reduce the number of cache misses incurred (or I/Os performed) by the computation over that performed by standard GEP by a factor of √ M, where M is the size of the cache. Cache-oblivious I-GEP computes in-place and solves most of the known applications of GEP including Gaussian elimination and LU-decomposition without pivoting and Floyd-Warshall all-pairs shortest paths. Cache-oblivious C-GEP uses a modest amount of additional space, but is completely general and applies to any code in GEP form. Both I-GEP and C-GEP produce system-independent cacheefficient code, and are potentially applicable to being used by optimizing compilers for loop transformation.We present parallel I-GEP and C-GEP that achieve good speed-up and match the sequential caching performance cache-obliviously for both shared and distributed caches for sufficiently large inputs.We present extensive experimental results for both in-core and out-of-core performance of our algorithms. We consider both sequential and parallel implementations, and compare them with finely-tuned cache-aware BLAS code for matrix multiplication and Gaussian elimination without pivoting. Our results indicate that cacheoblivious GEP offers an attractive trade-off between efficiency and portability.This work was supported in part by NSF Grant CCF-0514876 and NSF CISE Research Infrastructure Grant EIA-0303609. This journal submission incorporates results on the cache-oblivious paradigm that were presented in preliminary form in [8] and [9].

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Autotuning divide‐and‐conquer stencil computations

Natarajan

Dehnavi

Leiserson

2017

Concurrency and Computation

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Summary This paper explores autotuning strategies for serial divide‐and‐conquer stencil computations, comparing the efficacy of traditional “heuristic” autotuning with that of “pruned‐exhaustive” autotuning. We present a pruned‐exhaustive autotuner called Ztune that searches for optimal divide‐and‐conquer trees for stencil computations. Ztune uses three pruning properties—space‐time equivalence, divide subsumption, and favored dimension—that greatly reduce the size of the search domain without significantly sacrificing the quality of the autotuned code. We compared the performance of Ztune with that of a state‐of‐the‐art heuristic autotuner called OpenTuner in tuning the divide‐and‐conquer algorithm used in Pochoir stencil compiler. Over a nightly run on ten application benchmarks across two machines with different hardware configurations, the Ztuned code ran 5% –12% faster on average, and the OpenTuner tuned code ran from 9% slower to 2% faster on average, than Pochoir's default code. In the best case, the Ztuned code ran 40% faster, and the OpenTuner tuned code ran 33% faster than Pochoir's code. Whereas the autotuning time of Ztune for each benchmark could be measured in minutes, to achieve comparable results, the autotuning time of OpenTuner was typically measured in hours or days. Surprisingly, for some benchmarks, Ztune actually autotuned faster than the time it takes to perform the stencil computation once.

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The cache complexity of multithreaded cache oblivious algorithms

Cited by 44 publications

References 27 publications

Scheduling irregular parallel computations on hierarchical caches

Scheduling irregular parallel computations on hierarchical caches

The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation

Autotuning divide‐and‐conquer stencil computations

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