The cache and memory subsystems of the IBM POWER8 processor

Starke, William J.; Stuecheli, Jeffrey; Daly, David; Dodson, J. S.; Auernhammer, Florian; Sagmeister, Patricia; Guthrie, Guy L.; Marino, Charles F.; Siegel, M. S.; Blaner, B.

doi:10.1147/jrd.2014.2376131

Cited by 49 publications

(27 citation statements)

References 16 publications

(24 reference statements)

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“…Each POWER8 core owns a store-through L1 data cache, a store-in L2 cache, and an eDRAM based L3 cache with a capacity of 64 KB, 512 KB, and 8 MB, respectively. The L3 caches of POWER8 have a NUCA (NonUniform Cache Architecture) design, with each L3 also serving requests for other cores, and working as a victim cache for other L3s [26]. Additionally, the POWER8 processor is connected to a maximum of eight external memory buffer chips called Centaur.…”

Section: Overview Of Power8mentioning

confidence: 99%

Optimizing Sparse Matrix-Vector Multiplication for Large-Scale Data Analytics

Buono

Petrini

Checconi

et al. 2016

Proceedings of the 2016 International Conference on Supercomputing

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Sparse Matrix-Vector multiplication (SpMV) is a fundamental kernel, used by a large class of numerical algorithms. Emerging big-data and machine learning applications are propelling a renewed interest in SpMV algorithms that can tackle massive amount of unstructured data-rapidly approaching the TeraByte range-with predictable, high performance. In this paper we describe a new methodology to design SpMV algorithms for shared memory multiprocessors (SMPs) that organizes the original SpMV algorithm into two distinct phases. In the first phase we build a scaled matrix, that is reduced in the second phase, providing numerous opportunities to exploit memory locality. Using this methodology, we have designed two algorithms. Our experiments on irregular big-data matrices (an order of magnitude larger than the current state of the art) show a quasi-optimal scaling on a large-scale POWER8 SMP system, with an average performance speedup of 3.8×, when compared to an equally optimized version of the CSR algorithm. In terms of absolute performance, with our implementation, the POWER8 SMP system is comparable to a 256-node cluster. In terms of size, it can process matrices with up to 68 billion edges, an order of magnitude larger than state-of-the-art clusters. CCS Concepts•Computing methodologies → Linear algebra algorithms; Shared memory algorithms; Vector / streaming algorithms; •Mathematics of computing → Graph algorithms; •Theory of computation → Graph algorithms analysis; Data structures design and anal- * Fabrizio Petrini has since changed his affiliation. His current contact is fabrizio.petrini@intel.com ACM acknowledges that this contribution was authored or co-authored by an employee, or contractor of the national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only. Permission to make digital or hard copies for personal or classroom use is granted. Copies must bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. To copy otherwise, distribute, republish, or post, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org.

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Section: Overview Of Power8mentioning

confidence: 99%

Optimizing Sparse Matrix-Vector Multiplication for Large-Scale Data Analytics

Buono

Petrini

Checconi

et al. 2016

Proceedings of the 2016 International Conference on Supercomputing

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“…On the POWER8 processor chip, the PCIe Host Bridge (PHB) provides connectivity to PCIe Gen3 I/O links. The Coherent Accelerator Processor Proxy (CAPP) unit, in conjunction with the PHB, act as memory coherence, data transfer, interrupt, and address translation agents on the SMP interconnect [9] fabric for PCIe-attached accelerators. These accelerators comprise a POWER Service Layer (PSL) and Accelerator Function Units (AFUs) that reside in an FPGA or ASIC connected to the processor chip by the PCIe Gen3 link.…”

Section: Capi System Descriptionmentioning

confidence: 99%

“…The CAPP structures and machines parallel those of the L2 cache directory described in [9], while the data-portion of the cache is maintained by the PSL. Figure 2 shows the CAPP hardware in greater detail.…”

Section: Capp Hardware Descriptionmentioning

confidence: 99%

“…Assume a particular memory controller responds as owning the memory address of the line. The cresp contains information for routing the data to the memory controller [9]. Master FSM 0 sends this routing information to the PHB via the PHB sideband interface so that when the data packet containing the modified cache line arrives from the PSL, the PHB may push the line on its data_out bus directly to that particular memory controller.…”

Section: Capp Hardware Descriptionmentioning

confidence: 99%

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CAPI: A Coherent Accelerator Processor Interface

Stuecheli¹,

Blaner²,

Johns³

et al. 2015

IBM J. Res. & Dev.

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148

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Heterogeneous computing systems combine different types of compute elements that share memory. A specific class of heterogeneous systems discussed in this paper pairs traditional general-purpose processing cores and accelerator units. While this arrangement enables significant gains in application performance, device driver overheads and operating system code path overheads can become prohibitive. The I/O interface of a processor chip is a well-suited attachment point from a system design perspective, in that standard server models can be augmented with application-specific accelerators. However, traditional I/O attachment protocols introduce significant device driver and operating system software latencies. With the Coherent Accelerator Processor Interface (CAPI), we enable attaching an accelerator as a coherent CPU peer over the I/O physical interface. The CPU peer features consist of a homogeneous virtual address space across the CPU and accelerator, and hardware-managed caching of this shared data on the I/O device. This attachment method greatly increases the opportunities for acceleration due to the much shorter software path length required to enable its use compared to a traditional I/O model.

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“…As described in a later section of this paper, the fabrication of the broad device suite offerings is more straightforward and fabricated with larger process robustness. This enables a full-featured system-on-chip (SoC) capability with confident yield projections and compact model projections, making possible a range of first-time-right analog functions to support both the processor and the memory buffer chip [3].…”

Section: Introductionmentioning

confidence: 99%

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

et al. 2015

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IBM's high-performance 22-nm silicon-on-insulator (SOI) technology is the enabling physical foundation of IBM POWER8i processors. This paper describes, for the first time in detail, some of the unique aspects of the silicon processing, the features that enabled the industry-leading chip-level performance, and some aspects of the collaborative approach between technology and design teams that enabled both first-time-right silicon and rapid yield improvement. Most critical to the processor functional capability and power-performance achievements are the high-density on-chip memory in the form of embedded DRAM and the high-performance FET device designs based on a low-parasitic-capacitance gate-first FET architecture. Extensive on-chip analog functions are enabled by an additional comprehensive set of devices available in the technology. Fifteen levels of metal with five metal levels at an 80-nm pitch provide the interconnect and power distribution. We describe the pattern resolution enhancement strategy as well as motivation and structural aspects of the innovative features, from the low-resistance N+ epitaxy substrate under the SOI to a dual-embedded source-drain architecture and a highly scaled gate dielectric.

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The cache and memory subsystems of the IBM POWER8 processor

Cited by 49 publications

References 16 publications

Optimizing Sparse Matrix-Vector Multiplication for Large-Scale Data Analytics

Optimizing Sparse Matrix-Vector Multiplication for Large-Scale Data Analytics

CAPI: A Coherent Accelerator Processor Interface

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

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