The Blue Gene/L Supercomputer: A Hardware and Software Story

Moreira, José E.; Salapura, Valentina; Almási, George; Archer, Charles J; Bellofatto, R.; Bergner, Peter; Bickford, R.; Blumrich, Matthias A.; Brunheroto, José R.; Bright, A. A.; Brutman, Michael; Castaños, José G.; Dong, Chen; Coteus, P.; Crumley, P.; Ellis, S.; Engelsiepen, Thomas; Gara, Alan; Giampapa, Mark; Gooding, Tom; Hall, Shawn A.; Haring, R.A.; Haskin, Roger L.; Heidelberger, Philip; Hoenicke, D.; Inglett, Todd; Kopcsay, G. V.; Lieber, Derek; McCarthy, P.; Megerian, Mark; Mundy, Michael B.; Ohmacht, Martin; Parker, Jeff; Rand, R.; Reed, Don; Sahoo, Ramendra K.; Sanomiya, A.; Shok, Richard; Smith, Brian E.; Stewart, Gordon G.; Takken, Todd; Vranas, P.; Wallenfelt, Brian; Blocksome, Michael A; Ratterman, Joe

doi:10.1007/s10766-007-0037-2

Cited by 9 publications

(4 citation statements)

References 25 publications

(34 reference statements)

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“…From 1992, this value is constantly above 10, which shows a recent tendency for articles to have tens of authors. The article written by Moreira et al (2007) lists 46 co-authors, which is the maximum for our sample. The results, shown in Table 3, for conference articles and journal articles, considered separately, are similar to the overall results but with some relevant differences.…”

Section: Results Based On the Number Of Authorsmentioning

confidence: 99%

Authorship trends in software engineering

Fernandes

2014

Scientometrics

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This paper aims to examine authorship trends in software engineering, especially those related to the number of authors, of scientific publications. We collected and mined around 70.000 entries from DBLP for 122 conferences and journals, for the period 1971-2012, in order to process several bibliometric indicators. We provide evidence that the number of authors of articles in software engineering is increasing on average around ?0.40 authors/decade. The results also indicate that until 1980, the majority of the articles have a sole author, while nowadays articles with 3 or 4 authors represent almost half of the total.

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Section: Results Based On the Number Of Authorsmentioning

confidence: 99%

Authorship trends in software engineering

Fernandes

2014

Scientometrics

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“…the user interface, configuration logic, etc.-That is why most of the times the memory address translation features -e.g. virtual-to-physical mapping units or MMUs -of commercial processors, even if available, can be turned off, as is the case on most embedded operating systems (vxWorks, uCLinux) or even IBM BlueGene/L [4]. Having this in mind, the DNP has been optimized for the no-memory address translation case, making it comparatively small in size and relatively scarce in used silicon resources, opening the possibility to put multiple DNP instances onto the same chip.…”

Section: Introductionmentioning

confidence: 99%

The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture

Biagioni¹,

Cicero²,

Lonardo³

et al. 2012

Preprint

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One of the most demanding challenges for the designers of parallel computing architectures is to deliver an efficient network infrastructure providing low latency, high bandwidth communications while preserving scalability. Besides off-chip communications between processors, recent multi-tile (i.e. multi-core) architectures face the challenge for an efficient on-chip interconnection network between processor's tiles. In this paper, we present a configurable and scalable architecture, based on our Distributed Network Processor (DNP) IP Library, targeting systems ranging from single MPSoCs to massive HPC platforms.The DNP provides inter-tile services for both on-chip and offchip communications with a uniform RDMA style API, over a multi-dimensional direct network -see [1] for a definition of direct networks -with a (possibly) hybrid topology. It is designed as a parametric Intellectual Property Library easily customizable to specific needs. The currently available blocks implement wormhole, deadlock-free packet-based communications with static routing.The DNP offers a configurable number L, N and M of ports -respectively intra-tile I/O ports to ensure connections among elements within the same computational tile, on-chip communication ones to link different tiles onto the same silicon die, and off-chip communication inter-tile I/O ports to link those belonging to different dies. -Because of the fully switched architecture, the DNP may sustain up to L + N + M packet transactions at the same time.The DNP has been integrated into the design of an MPSoC dedicated to both high performance audio/video processing and theoretical physics applications. We present the details of its architecture and show some promising results we obtained on a first preliminary implementation.

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“…The guiding design principles for Blue Gene are simplicity, efficiency, and familiarity [5]. Regarding energy efficiency, the key feature of Blue Gene is its judiciously chosen low-frequency, low-voltage design which results in both high-performance and highly energy-efficient supercomputers.…”

Section: Introductionmentioning

confidence: 99%

Measuring power consumption on IBM Blue Gene/P

Hennecke¹,

Frings

Homberg

et al. 2011

Comput Sci Res Dev

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Energy efficiency is a key design principle of the IBM Blue Gene series of supercomputers, and Blue Gene systems have consistently gained top GFlops/Watt rankings on the Green500 list. The Blue Gene hardware and management software provide built-in features to monitor power consumption at all levels of the machine's power distribution network. This paper presents the Blue Gene/P power measurement infrastructure and discusses the operational aspects of using this infrastructure on Petascale machines. We also describe the integration of Blue Gene power monitoring capabilities into system-level tools like LLview, and highlight some results of analyzing the production workload at Research Center Jülich (FZJ).

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The Blue Gene/L Supercomputer: A Hardware and Software Story

Cited by 9 publications

References 25 publications

Authorship trends in software engineering

Authorship trends in software engineering

The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture

Measuring power consumption on IBM Blue Gene/P

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