The base-line DataFlow system of the ATLAS trigger and DAQ

Beck, H. P.; Abolins, M.; Anjos, A. Dos; Barisonzi, M.; Beretta, M.; Blair, Robert; Bogaerts, J. A.; Boterenbrood, H.; Botterill, D.; Ciobotaru, M. D.; Cortezon, E. Palencia; Cranfield, R.; Crone, G.; Dawson, J. W.; Girolamo, B. Di; Dobinson, R.; Ermoline, Y.; Ferrer, M. L.; Francis, D.; Gadomski, S.; Gameiro, S.; Golonka, P.; Gorini, B.; Green, B.; Gruwé, M.; Haas, S.; Haeberli, C.; Hasegawa, Yohei; Hauser, R.; Hinkelbein, C.; Hughes-Jones, R. E.; Knezo, E.; Jansweijer, P.; Joos, M.; Kaczmarska, A.; Kieft, G.; Korcyl, K.; Kugel, A.; Lankford, A.J.; Lehmann, G.; LeVine, M. J.; Liu, Weiyue; Maeno, T.; Maia, M.L.; Mapelli, L.; Martin, B.; McLaren, R. A.; Meiroşu, Cătălin; Misiejuk, A.; Mommsen, R. K.; Mornacchi, G.; Müller, Matthias; Nagasaka, Y.; Nakayoshi, K.; Papadopoulos, I.; Petersen, J.; Pinto, P.; Prigent, Daniel; Reale, V. Perez; Schlereth, J. L.; Shimojima, M.; Spiwoks, R.; Stancu, S.; Strong, J. A.; Tremblet, L.; Vermeulen, J. C.; Werner, P.; Wickens, F. J.; Yasu, Y.; Yu, Maoyuan; Zobernig, H.; Zurek, M.

doi:10.1109/tns.2004.828707

Cited by 20 publications

(4 citation statements)

References 5 publications

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“…The S-LINK is a CERN specification for FIFO-like data-link which can be used to connect front-end to read-out in a data flow environment. The PCIe S-LINK card is mounted on the SROD PC and sends data to the ATLAS readout system [9]. This card also has LEMO connectors to send the busy signal from the SROD by open-drain to the TTC FAN-OUT BOARD.…”

Section: Development Of the New Trigger Processor Board For The Atlasmentioning

confidence: 99%

Development of the New Trigger Processor Board for the ATLAS Level-1 Endcap Muon Trigger for Run-3

Mizukami¹

2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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The instantaneous luminosity of the LHC will be increased by up to a factor of three with respect to the original design value at Run-3 (starting 2021). The ATLAS Level-1 end-cap muon trigger in LHC Run-3 will identify muons by combining data from the Thin-Gap Chamber detector (TGC) and the New Small Wheel (NSW), which is a new detector and will be able to operate in a high background hit rate at Run-3, to suppress the Level-1 trigger rate. In order to handle data from both TGC and NSW, a new trigger processor board has been developed. The board has a modern FPGA to make use of Multi-Gigabit transceiver technology. The readout system for trigger data has also been designed with TCP/IP instead of a dedicated ASIC. This letter presents the electronics and its firmware of the ATLAS Level-1 end-cap muon trigger processor board for LHC Run-3.

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Section: Development Of the New Trigger Processor Board For The Atlasmentioning

confidence: 99%

Development of the New Trigger Processor Board for the ATLAS Level-1 Endcap Muon Trigger for Run-3

Mizukami¹

2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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“…The Information Sharing package provides the infrastructure to obtain and publish information on the status of the controlled system, to report and receive error messages, and to publish results for interaction with the operator. [4], [5]. Read out system run on Timesys real time Linux/ PowerPC, read data, pack to event and send to back-end.…”

Section: A Online Software Designmentioning

confidence: 99%

DAQ architecture design of Daya Bay Reactor Neutrino Experiment

2010

2010 17th IEEE-NPSS Real Time Conference

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Abstract-The main task of the data acquisition (DAQ) system in Daya Bay Reactor Neutrino Experiment is to record antineutrino candidate events and other background events. There are seventeen detectors in three sites. Each detector will have a separate VME readout crate that contains the trigger and DAQ electronics modules. The DAQ system reads event data from front end electronics modules, concatenates data fragments of the modules and packs them to a subsystem event, then transmits to the backend system to do data stream merging, monitoring and recording.The DAQ architecture design is a multi-level system using advanced commercial computers and the network technology. The architecture requires multiple independent or part joint DAQ systems at each site. The run control will be configurable and flexible; it should allow both global operation of all detector systems in all three sites, and operations of parts of detectors whenever debugging or commissioning is required. The system should allow each subsystem in any detector site to start its own run control so that debugging and commissioning can be conducted in parallel. This paper presents the main DAQ design requirements, the system architecture design and the software architecture design.

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“…The standard route for read-out data in ATLAS is through a detector specific Read-out Driver (ROD) into a ROBIN on a ROS system via a Slink fibre [8].…”

Section: Read-out Data To Atlas Read-out System (Ros)mentioning

confidence: 99%