The art of multiprocessor programming

Abstract

Computer architecture is about to undergo, if not another revolution, then a vigorous shaking-up. The major chip manufacturers have, for the time being, simply given up trying to make processors run faster. Instead, they have recently started shipping "multicore" architectures, in which multiple processors (cores) communicate directly through shared hardware caches, providing increased concurrency instead of increased clock speed.As a result, system designers and software engineers can no longer rely on increasing clock speed to hide software bloat. Instead, they must somehow learn to make effective use of increasing parallelism. This adaptation will not be easy. Conventional synchronization techniques based on locks and conditions are unlikely to be effective in such a demanding environment. Coarse-grained locks, which protect relatively large amounts of data, do not scale, and fine-grained locks introduce substantial software engineering problems.Transactional memory is a computational model in which threads synchronize by optimistic, lock-free transactions. This synchronization model promises to alleviate many (not all) of the problems associated with locking, and there is a growing community of researchers working on both software and hardware support for this approach. This talk will survey the area, with a focus on open research problems.

SMV: Selective Multi-Versioning STM

“…Commit (lines [15][16][17][18][19][20][21][22][23][24][25][26][27][28] consists of the following steps:…”

“…Read-only transactions play a significant role in various types of applications, including linearizable data structures with a strong prevalence of read-only operations [17], or client-server applications where an STM infrastructure replaces a traditional DBMS approach (e.g., FenixEDU web application [9]). Particularly long read-only transactions are employed for taking consistent snapshots of dynamically updated systems, which are then used for checkpointing, process replication, monitoring program execution, gathering system statistics, etc.…”

Implementation of Massive Artificial Neural Networks with CUDA

“…The practice of parallel programming is not something new, it has been in use for decades. However, these programs run on large scale and expensive computers (see Herlihy & Shavit, 2008). With recent evolution of GPUs, massive programming has become available for everyone.…”

CAFÉ: Scalable Task Pools with Adjustable Fairness and Contention

“…Unless stated otherwise, we use h = 12. -CLQ -The standard Java 6 implementation of a (FIFO) non-blocking queue by Michael and Scott [7] (class java.util.concurrent.ConcurrentLinkedQueue, which is considered to be one of the most efficient non-blocking algorithms in the literature [5,6]. -LBQ -The standard Java 6 implementation of a (FIFO) blocking queue that uses a global reader-writer lock (class java.util.concurrent.LinkedBlockingQueue).…”

“…4 One task overtakes another task if it is inserted after the other task, but retrieved before it. 5 A randomized algorithm is wait-free if each thread executing an operation performs a finite number of steps with probability 1.…”