The approach to multiple instruction execution in the GMICRO/400 processor

Yoshida, Toyohiko; Matsuo, M.; Iwata, S.

doi:10.1109/tron.1991.213104

Cited by 8 publications

(1 citation statement)

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“…We have developed a 32-bit superscalar microprocessor GMICR0/400, based on the TRON architecture specifications [3]. This processor focuses on embedded system use, such as X-window terminals and printers.…”

Section: Introductionmentioning

confidence: 99%

A 32-bit superscalar microprocessor G/sub MICRO//400 for embedded systems

Korematsu

Ueda

Matsuo

et al.

Proceedings of the 11th TRON Project International Symposium

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This paper describes a 32-bit superscalar microprocessor GMICRO/4OO, based on the TRON architecture specifications. The GM1C~0/400 has a dual issued instruction pipeline, a pre-jump mechanism and a high-speed memory access interface. To realize high performance in processing of series data such as frame buffer o r character-strings, the GMICRO/400 has improved the execution efficiency of multiple-operation instructions by blockdata-transfer and Wbit processing. In order to improve the task switching latency, the onchip caches are used as a local memory in which the context blocks are stored. These techniques are suitable for realtime embedded systems, such as X-window terminals and printers.Using 05pm triple-layer metal CMOS technology, the GMICRO/4OO integrates 1485K transistors on a 108mm2 die area. The Gh11C~0/400 achieves a processing speed of 45 MIPS at 40MHz.

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Section: Introductionmentioning

confidence: 99%