The application of bit-serial CORDIC computational units to the design of inverse kinematics processors

Harber, R.G.; Hu, Xiaofang; Li, J.; Bass, S.

doi:10.1109/robot.1988.12217

Cited by 23 publications

(5 citation statements)

References 5 publications

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“…From Fig. 4b, it can be concluded that the computing time of the parallel inverse kinematic processor is about 16 tcor comparing to 23 tcor for the serial inverse kinematic processor [9], where t,,, is the execution time of a CORDIC processor. There are three l-bit indicators which indicate there exist 8 possible solutions corresponding to a given hand position and orientation.…”

Section: Parallel Inverse Kinematicsmentioning

confidence: 93%

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Parallel algorithm and VLSI architecture for a robot's inverse kinematics

Lai

Chao

1989

Proceedings of the 1989 ACM/IEEE Conference on Supercomputing - Supercomputing '89

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The inverse solutions of a robotic systems are generally produced by a serial process. Due to the computing time of processing geometry data and generating an inverse solution corresponding to a specified point in Cartesian trajectory is larger than the sampling period, the missing points in the joint space are generated by some interpolation schemes ( linear or cubic spline interpolations ) between two inverse solutions.The dynamic errors are therefore introduced.Obviously this kind of dynamic errors can be eliminated, if the computational time of generating the inverse solutions and processing geometric information can be less than the sampling period. The dynamic errors are increased when a robot's speed is increased by using the available schemes. For a high speed and high performance robot, the dynamic errors can be significant.In this paper, a parallel algorithm for a robot's inverse kinematics is derived and corresponding VLSI architectures are presented. This algorithm can also be implemented by using multiprocessors.By using the proposed parallel algorithm, it is believed that the dynamic errors can be reduced significantly or even eliminated if the computing time of processing geometric data can be reduced significantly by using the technique of parallel processing.

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Section: Parallel Inverse Kinematicsmentioning

confidence: 93%

“…For eliminating the dynamic errors and meeting the real time relquirement, Lee and Chang [7], Wang and Butner [8], and Harbes et al [9] proposed that the serial version of inverse kinematics, Eq. (2), can be implemented on a chip by using CORDIC processors.…”

Section: Introductionmentioning

confidence: 99%

Parallel algorithm and VLSI architecture for a robot's inverse kinematics

Lai

Chao

1989

Proceedings of the 1989 ACM/IEEE Conference on Supercomputing - Supercomputing '89

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“…Recent advances in VLSI have allowed the mapping of complex algorithms to hardware using systolic arrays with advanced computer arithmetic algorithms such as CORDIC algorithm. CORDIC have been used in robotics for inverse kinematics (Harber et al, 1988;Kameyama et al, 1989;Lee and Chang, 1987), for nonredundant robots and for control (Butner et al, 1988;Wang and Butner, 1987). According to Walker and Cavallaro (1994), CORDIC arithmetic in the novel design of special-purpose VLSI array, forming a key part of an efficient architecture for redundant robot kinematics computations.…”

Section: Methodsmentioning

confidence: 99%

Low Energy, Improved Speed and High Throughput CORDIC Cell to Improve Performance of Robots’ Processor

Velrajkuma¹,

Senthilpar²,

Murthy³

et al. 2015

Asian J. of Scientific Research

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Robots are used in various real-time applications. The speed constraint in robotic system applications requires a real-time interface operation; this is a recent target in robotic research. The cost and size of a robotic system is often determined by hardware-based solutions. The coordinate Rotation Digital Computer (CORDIC) technique allows for an efficient execution of functions, such as inverse tangents and vector rotations, in the hardware. The CORDIC algorithm is very well suited for VLSI implementation due to the simplicity of the involved operations. This study proposed a full-adder based bit parallel iterative CORDIC circuit to improve the performance of robots' processor. The proposed full-adder and CORDIC circuit are designed and their layouts are generated by VLSI CAD tool. The parametric analysis is done using by BSIM4 analyzer. The output parameters such as propagation delay, area and power dissipation are calculated from simulated results of CORDIC cell. The proposed adder based CORDIC circuit designed for low energy, improved speed, low EPI and high throughput. The simulated result of proposed adder based CORDIC circuit is compared with other published CORDIC circuits. From the analysis of these simulated results, it was found that proposed adder based CORDIC circuit gives better performance in terms of power, propagation delay, speed, EPI and throughput than other published results. The results are extended to analysis of temperature coefficient, thermal conductivity and thermal flux for CORDIC cells' chip. The proposed circuit gives better tolerance of temperature and less leakage current than other adder based CORDIC cell.

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“…The authors in [101] present a maximum pipelined CORDIC-based architecture for efficient computation of the inverse kinematics solution. It is also shown [101], [102] that up to 25 CORDIC processors are required for the computation of the entire inverse kinematics solution for a six-link PUMA-type robotic arm. Apart from implementation of rotation operations, CORDIC is used in the evaluation of trigonometric functions and square root expressions involved in the inverse kinematics problems [103].…”

Section: ) Direct Kinematics Solution (Dks) For Serial Robot Manipulmentioning

confidence: 99%