The Alpha 21264: a 500 MHz out-of-order execution microprocessor

Leibholz, D.; Razdan, Rahul

doi:10.1109/cmpcon.1997.584667

Cited by 42 publications

(31 citation statements)

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“…Common methods for restoring the map [11,19]. On a misprediction, the checkpoint corresponding to the mispredicted branch is restored.…”

Section: Impact Of Misprediction Recovery Mechanismmentioning

confidence: 99%

“…Branch misprediction recovery requires redirecting fetch to the correct instruction and restoring the rename map table before new instructions can be renamed. The map table can be restored from a checkpoint [11,19], incrementally restored from a non-speculative map table such as the retirement register alias table [6], or incrementally restored from a history buffer that stores the speculative map table updates performed since the mispredicted branch was dispatched. In Section 3.2, we show practical implementations of these traditional recovery mechanisms to be either too costly or too slow and in Section 4.1 we present a new policy of checkpointing the map table at lowconfidence branches.…”

Section: Introductionmentioning

confidence: 99%

“…Their proposal also did not employ a ROB but rather used checkpoints at conditional branches to restore state. The Pentium 4 uses a retirement register alias table to track maps [6] while the MIPS R10000 [19] and Alpha 21264 [11] use a checkpoint method to recover rename maps. The checkpoint method as used by the MIPS R10000 and Alpha 21264 do not scale as instruction windows become larger.…”

Section: Related Workmentioning

confidence: 99%

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Checkpoint processing and recovery: towards scalable large instruction window processors

Akkary¹,

Rajwar²,

Srinivasan³

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

179

263

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“…Common methods for restoring the map [11,19]. On a misprediction, the checkpoint corresponding to the mispredicted branch is restored.…”

Section: Impact Of Misprediction Recovery Mechanismmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Checkpoint processing and recovery: towards scalable large instruction window processors

Akkary¹,

Rajwar²,

Srinivasan³

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

179

263

View full text Add to dashboard Cite

show abstract

“…Loads waiting for a store instruction must wait for the store's address and data value register to be ready before issuing. 1 For some loads, the additional delay of the false dependence will be hidden by the out-of-order execution engine. Other loads will be on the critical path and the unnecessary delay will have a direct impact on performance.…”

Section: No Speculationmentioning

confidence: 99%

“…Modern superscalar processors such as the Alpha 21264 [1], MIPS R10000 [2], HP-PA8000 [3] and Intel Pentium Pro [4], allow instructions to execute out of program order to find more instruction level parallelism (ILP). These processors must monitor data dependencies to maintain correct program behavior.…”

Section: Introductionmentioning

confidence: 99%

Memory dependence prediction using store sets

Chrysos

Emer

1998

SIGARCH Comput. Archit. News

109

175

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Verification of an implementation of Tomasulo's algorithm by compositional model checking

McMillan

1998

Lecture Notes in Computer Science

109

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An implementation of an out-of-order processing unit based on Tomasulo's algorithm is formally verified using compositional model checking techniques. This demonstrates that finite-state methods can be applied to such algorithms, without recourse to higher-order proof systems. The paper introduces a novel compositional system that supports cyclic environment reasoning and multiple environment abstractions per signal. A proof of Tomasulo's algorithm is outlined, based on refinement maps, and relying on the novel features of the compositional system. This proof is fully verified by the SMV verifier, using symmetry to reduce the number of assertions that must be verified. IntroductionWe present the formal design verification of an "out-of-order" processing unit based on Tomasulo's algorithm [Tom67]. This and related techniques such as "register renaming" are used in modern microprocessors [LR97] to keep multiple or deeply pipelined execution units busy by executing instructions in data-flow order, rather than sequential order. The complex variability of instruction flow in "out-of-order" processors presents a significant opportunity for undetected errors, compared to an "in-order" pipelined machine where the flow of instructions is fixed and orderly. Unfortunately, this variability also makes formal verification of such machines difficult. They are beyond the present capacity of methods based on integrated decision procedures [BD94], and are not amenable to symbolic trajectory analysis [JNB96]. This paper was inspired by Damm and Pnueli, who recently presented a pencil-and-paper proof of an implementation of Tomasulo's algorithm [DP97]. This proof is in two stages, first refining a sequential specification to an intermediate model based on partially ordered executions, and then refining this model to the implementation. The proof presented here has several advantages over this earlier work. First, it is conceptually simpler, since we refine the specification directly to the implementation, with no intermediate step, and no need to reason about second-order objects such as sets or partial orders. Second, the proof here is fully mechanically checked, using a verifier based on symbolic model checking. Although in principle, the proof of [DP97] can be carried out in a higher order prover such as PVS [ORSS94], this would require considerable elaboration. Here, the use of model checking to handle the details of the proof allows the proof to be presented here in the same form in which it is actually presented to the verifier. Third, the implementation here is at the bit level,

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The Alpha 21264: a 500 MHz out-of-order execution microprocessor

Cited by 42 publications

References 1 publication

Checkpoint processing and recovery: towards scalable large instruction window processors

Checkpoint processing and recovery: towards scalable large instruction window processors

Memory dependence prediction using store sets

Verification of an implementation of Tomasulo's algorithm by compositional model checking

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