The Accelerator Store framework for high-performance, low-power accelerator-based systems

Lyons, Michael J.; Hempstead, Mark; Wei, Gu-Yeon; Brooks, David

doi:10.1109/l-ca.2010.16

Cited by 44 publications

(81 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1. On average, 62.20% of the tile area is devoted to memory, which is consistent with the survey in [13]. The cache manager takes on average 7.89% of a tile's area.…”

Section: Area and Power Consumptionsupporting

confidence: 84%

“…Given the predicted fall of multicore scaling at the hands of dark silicon [5], superior efficiency via specialization has materialized as a compelling solution toward sustaining performance gains [16]; once restricted to embedded systems, accelerators are currently seeing wider exposure (e.g., [3]), and many-accelerator architectures are in the research agenda ( [4], [13]). …”

Section: Introductionmentioning

confidence: 99%

“…A survey of eleven publicly available accelerators reveals that "an average of 69% of accelerator area is consumed by memory" [13], which makes memory the best candidate for reuse among accelerator components.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Accelerator Memory Reuse in the Dark Silicon Era

Cota

Mantovani

Petracca

et al. 2014

IEEE Comput. Arch. Lett.

View full text Add to dashboard Cite

Abstract-Accelerators integrated on-die with General-Purpose CPUs (GP-CPUs) can yield significant performance and power improvements. Their extensive use, however, is ultimately limited by their area overhead; due to their high degree of specialization, the opportunity cost of investing die real estate on accelerators can become prohibitive, especially for general-purpose architectures. In this paper we present a novel technique aimed at mitigating this opportunity cost by allowing GP-CPU cores to reuse accelerator memory as a non-uniform cache architecture (NUCA) substrate. On a system with a last level-2 cache of 128kB, our technique achieves on average a 25% performance improvement when reusing four 512 kB accelerator memory blocks to form a level-3 cache. Making these blocks reusable as NUCA slices incurs on average in a 1.89% area overhead with respect to equally-sized ad hoc cache slices.

show abstract

“…1. On average, 62.20% of the tile area is devoted to memory, which is consistent with the survey in [13]. The cache manager takes on average 7.89% of a tile's area.…”

Section: Area and Power Consumptionsupporting

confidence: 84%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Accelerator Memory Reuse in the Dark Silicon Era

Cota

Mantovani

Petracca

et al. 2014

IEEE Comput. Arch. Lett.

View full text Add to dashboard Cite

show abstract

“…In [8], Lyons et al propose an architecture to support systems with tens to hundreds of accelerators. They find accelerator area is dominated by SRAM and through the Accelerator Store they develop a way to share underutilized SRAM for little to no Cong et al present a design space trade-off study for reconfigurable FPGA-based high performance systems using a high-level synthesis tool [3].…”

Section: Related Workmentioning

confidence: 99%

Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

Reagen

Shao

Wei

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

Self Cite

View full text Add to dashboard Cite

Abstract-As the traditional performance gains of technology scaling diminish, one of the most promising directions is building special purpose fixed function hardware blocks, commonly referred to as accelerators. Accelerators have become prevalent in industrial SoC designs for their low power, high performance potential. In this work we explore thousands of implementations of classical software workloads in hardware. This thorough, detailed design space search of hardware accelerators gives architects a quantitative way to reason about the differences in implementations. The exploration presented in this work shows that the space is full of poor design choices. By thoroughly analyzing each benchmark, we show which provide the most performance when implemented in hardware given a fixed power budget and explain which design techniques work best for each workload.

show abstract

“…The body group investigates the design and manufacturing of an approximately 500 mg flapping-wing MAV including considerations of aerodynamics [1], artificial wings [2], actuation of wing stroke [3], control [4], passive stability [5], and power electronics [6]. The brain group is developing power efficient computational hardware and architectures [7] to enable high performance autonomous RoboBee algorithms. The colony group investigates algorithms for collective and emergent behavior of a group of RoboBees, despite minimal programming and communication between individuals [8].…”

Section: Introductionmentioning

confidence: 99%

Hardware in the loop for optical flow sensing in a robotic bee

Duhamel¹,

Porter²,

Finio³

et al. 2011

2011 IEEE/RSJ International Conference on Intelligent Robots and Systems

View full text Add to dashboard Cite

Abstract-The design of autonomous robots involves the development of many complex, interdependent components, including the mechanical body and its associated actuators, sensors, and algorithms to handle sensor processing, control, and high-level task planning. For the design of a robotic bee (RoboBee) it is necessary to optimize across the design space for minimum weight and power consumption to increase flight time; however, the design space of a single component is large, the interconnectedness and tradeoffs across components must be considered, and interdisciplinary collaborations cause different component design timelines.In this work, we show how the development of a hardware in the loop (HWIL) system for a flapping wing microrobot can simplify and accelerate evaluation of a large number of design choices. Specifically, we explore the design space of the visual system including sensor hardware and associated optical flow processing. We demonstrate the utility of the HWIL system in exposing trends on system performance for optical flow algorithm, field of view, sensor resolution, and frame rate.

show abstract

The Accelerator Store framework for high-performance, low-power accelerator-based systems

Cited by 44 publications

References 6 publications

Accelerator Memory Reuse in the Dark Silicon Era

Accelerator Memory Reuse in the Dark Silicon Era

Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

Hardware in the loop for optical flow sensing in a robotic bee

Contact Info

Product

Resources

About