The 4D-MP graphics superworkstation: computing+graphics=40 MIPS+MFLOPS and 100000 lighted polygons per second

Baskett, Forest; Jermoluk, Tom; Solomon, Daniela

doi:10.1109/cmpcon.1988.4913

Cited by 25 publications

(14 citation statements)

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“…Non-inclusive means that for any cache line in the L1 cache, it does not need to be in the L2 cache of the same chip. The cache state of MSI [5] or MESI [38] is used in each level. Also, features including silent dropping on non-modified cache lines and unordered network channels are modeled.…”

Section: Development Of Benchmark Hierarchical Protocolsmentioning

confidence: 99%

Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols

Chen

Yang

Gopalakrishnan

et al. 2010

Form Methods Syst Des

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Multicore architectures are considered inevitable, given that sequential processing hardware has hit various limits. Unfortunately, the memory system of multicore processors is a huge bottleneck. To combat this problem, one needs to design aggressively optimized cache coherence protocols. This introduces the design correctness problem for advanced cache coherence protocols which will be hierarchically organized for scalable designs. Experiences show that monolithic formal verification will not scale to hierarchical designs. Hence, one needs to handle the complexity of several coherence protocols running concurrently, i.e. hierarchical protocols, using compositional techniques.To solve the problem, we develop a family of compositional approaches all based on assume-guarantee reasoning to reducing the verification complexity. We show that for the three hierarchical protocols with certain realistic features that we developed for multiple chip-multiprocessors, more than a 20-fold improvement in terms of the number of states visited can be achieved. Also, to avoid false alarms wasting designer time, we have developed an error trace justification method to eliminate false alarms using heuristics that also capitalize on our assume-guarantee approaches. Our techniques need no special tool support. They can be carried out using the widely used Murphi model checker along with support tools for abstraction and error trace justification that we have built.

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Section: Development Of Benchmark Hierarchical Protocolsmentioning

confidence: 99%

Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols

Chen

Yang

Gopalakrishnan

et al. 2010

Form Methods Syst Des

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“…To this end, many different policies have been proposed, such as MSI [12], MOSI [11], MESI [13], or MOESI [11], as well as optimizations for migratory data [14].…”

Section: Related Workmentioning

confidence: 99%

Switch-based packing technique to reduce traffic and latency in token coherence

Cuesta

Robles

Duato

2012

Journal of Parallel and Distributed Computing

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Token Coherence is a cache coherence protocol able to simultaneously capture the best attributes of traditional protocols: low latency and scalability. However, it may lose these desired features when (1) several nodes contend for the same memory block and (2) nodes write highly-shared blocks. The first situation leads to the issue of simultaneous broadcast requests which threaten the protocol scalability. The second situation results in a burst of token responses directed to the writer, which turn it into a bottleneck and increase the latency. To address these problems, we propose a switch-based packing technique able to encapsulate several messages (while in transit) into just one. Its application to the simultaneous broadcasts significantly reduces their bandwidth requirements (up to 45%). Its application to token responses lowers their transmission latency (by 70%). Thus, the packing technique decreases both the latency and coherence traffic, thereby improving system performance (about 15% of reduction in runtime).

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“…It is very similar to the protocol that was used in the Silicon Graphics 4D series multiprocessor machines [23]. The MSI protocol defines three states, modified (M), shared (S), and invalid (I), to distinguish valid blocks that are unmodified (clean) from those that are modified (dirty).…”

Section: Msimentioning

confidence: 99%

Efficient techniques to provide scalability for token-based cache coherence protocols.

Sáez¹,

Antonio²

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The 4D-MP graphics superworkstation: computing+graphics=40 MIPS+MFLOPS and 100000 lighted polygons per second

Cited by 25 publications

References 0 publications

Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols

Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols

Switch-based packing technique to reduce traffic and latency in token coherence

Efficient techniques to provide scalability for token-based cache coherence protocols.

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