The 48-core SCC Processor: the Programmer's View

Abstract

The number of cores integrated onto a single die is expected to climb steadily in the foreseeable future. This move to many-core chips is driven by a need to optimize performance per watt. How best to connect these cores and how to program the resulting many-core processor, however, is an open research question. Designs vary from GPUs to cache-coherent shared memory multiprocessors to pure distributed memory chips. The 48-core SCC processor reported in this paper is an intermediate case, sharing traits of message passing and shared memory architectures. The hardware has been described elsewhere. In this paper, we describe the programmer's view of this chip. In particular we describe RCCE: the native message passing model created for the SCC processor.Index Terms-many-core processors, message passing APIs, non-cache-coherent shared memory.

Pronto: A Low Overhead Message Passing System for High Performance Many-Core Processors

“…The dataflow based Ambric Massively Parallel Processor Array [4] implements a similar methodology although with a hierarchical interconnect structure. The Intel SCC [7] on the other hand performs all required reservations at runtime rather than statically. Message passing is implemented through a global shared address space accessible through each PEs Message Passing Buffer (MPB).…”

Multi-objective mapping optimization via problem decomposition for many-core systems

“…Architecture: The target architecture is assumed to be hierarchical considering the recent design trend [14], [16], [18]. We maintain an abstract representation of this architecture, in a tree form, as depicted in Fig 4. For illustration, we restrict ourselves to only two levels of communication: (1) set of processors that form clusters communicating via a first level network, e.g., cluster (denoted cl x in Fig 4(b)) and (2) clusters connected via a second level network, e.g., on-chip network (g in Fig 4(b)).…”

“…That is, given the the task-to-cluster mapping, sort all the tasks that are mapped on a cluster cl (line 4-7). From the sorted list, the heaviest task is chosen (line 8) and assigned to the idlest processor in cl (line [13][14]. If the heaviest one does not fit to the idlest processor, this solution should be marked as invalid.…”

“…The Intel Single-chip Cloud Computer (SCC) [14] that has 24 clusters on a single die is considered as target platform. In SCC, each cluster has two pentium cores integrated and they communicate with each other via a shared memory.…”

“…While modern multimedia handheld devices as well as personal computers already have dual-or quadcore processors inside, the number of cores on a die keeps growing up to several dozens [14], [16], [18]. Moreover, the digital convergence trend is to have systems running multiple applications simultaneously in different combinations at different moments in time.…”