The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4

González, Christopher; Floyd, Michael S.; Fluhr, Eric; Restle, P.J.; Dreps, Daniel; Sperling, Michael; Rao, Rahul; Hogenmiller, David; Vezyrtis, Christos; Chuang, Pierce; Lewis, Daniel W.; Escobar, Ricardo Fernández; Ramadurai, Vinod; Kruse, Ryan C.; Pille, J.; Nett, Ryan; Owczarczyk, Pawel; Friedrich, Joshua; Paredes, Jose; Diemoz, Timothy; Islam, Saiful; Plass, D.; Muench, Paul

doi:10.1109/jssc.2017.2748623

Cited by 12 publications

(5 citation statements)

References 6 publications

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“…The OCC persists across the PowerNV platform from its launch with POWER8 to the latest POWER10 processors. However, the focused features shifted for the POWER9 processors: Gonzalez et al [12,13] describe it as a "scale-out (SO)" [12, Sec. II] processor, highlighting its input/output (IO) capabilities, namely a total 300 GB/s accelerator, 192 GB/s PCIeGen4 and 230 GB/s memory bandwidth.…”

Section: Power8 Power9 and The On-chip Controllermentioning

confidence: 99%

“…For simplicity, here we use a single sensor: The power consumption of the first processor (proc 0). 12 We assume that the OCC internally samples with 2 kSa/s (as the corresponding "sample time" is given with 500 µs in the specification [5, Sec. 11.3.2.2]), and that these samples are added without any further processing into the accumulator.…”

Section: Setup and Approachmentioning

confidence: 99%

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Evaluating the Energy Measurements of the IBM POWER9 On-Chip Controller

Tröpgen

Bielert

Ilsche

2023

Proceedings of the 2023 ACM/SPEC International Conference on Performance Engineering

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Dependable power measurements are the backbone of energyefficient computing systems. The IBM PowerNV platform offers such power measurements through an embedded PowerPC 405 processor: The On-Chip Controller (OCC). Among other system-control tasks, the OCC provides power measurements for several domains, such as system, CPU, and GPU. This paper provides a detailed description and an in-depth evaluation of these OCC-provided power measurements. For that, we describe the provided interfaces themselves and experimentally verify their overhead (3.6 µs to 10.8 µs per access) and readout rate (24.95 Sa/s). We also study the consistency of the reported sensor readouts across the measurement domains and compare it to externally measured data. Furthermore, we estimate the internal sampling rate (1996 Sa/s) by provoking aliasing errors with artificial workloads, and quantify the errors that such aliasing could introduce in practice (for power consumption of processors 12 % in our experimental worst-case scenario). Given these insights, practitioners using the IBM PowerNV platform can assess the quality of the embedded measurements, permitting sought-after energy efficiency improvements. CCS CONCEPTS• Hardware → Platform power issues; Chip-level power issues; Post-manufacture validation and debug; Energy metering.

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Section: Power8 Power9 and The On-chip Controllermentioning

confidence: 99%

Section: Setup and Approachmentioning

confidence: 99%

Evaluating the Energy Measurements of the IBM POWER9 On-Chip Controller

Tröpgen

Bielert

Ilsche

2023

Proceedings of the 2023 ACM/SPEC International Conference on Performance Engineering

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“…As each clock driver adds timing uncertainty, jitter (random variation in clock arrival time) and skew (spatial variation in clock arrival time) performances are also significantly impaired. As a result, both jitter and skew performances have been limited to several to tens ps range 1 , 5 , 8 , 10 . While the demand for higher data rates necessitates a tighter jitter and skew budget, clock skew and jitter deteriorate as on-chip process, voltage and temperature (PVT) variations worsen in deep sub-micron processes.…”

Section: Introductionmentioning

confidence: 99%

Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses

Hyun

Chung

et al. 2023

Nat Commun

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A clock distribution network (CDN) is a ubiquitous on-chip element that provides synchronized clock signals to all different circuit blocks in the chip. To maximize the chip performance, today’s CDN demands lower jitter, skew, and heat dissipation. Conventionally, on-chip clock signals have been distributed in the electric voltage domain, resulting in increased jitter, skew, and heat dissipation due to clock drivers. While low-jitter optical pulses have been locally injected in the chip, research on effective distribution of such high-quality clock signals has been relatively sparse. Here, we demonstrate femtosecond-precision distribution of electronic clocks using driver-less CDNs injected by photocurrent pulses extracted from an optical frequency comb source. Femtosecond-level on-chip jitter and skew can be achieved for gigahertz-rate clocking of CMOS chips by combining ultralow comb-jitter, multiple driver-less metal-meshes, and active skew control. This work shows the potential of optical frequency combs for distributing high-quality clock signals inside high-performance integrated circuits, including 3D integrated circuits.

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“…With the scale of CMOS technology, the performance of digital circuits improved dramatically [1,2]. However, analog circuits suffer from Signal Noise Ratio (SNR) reduction due to the decrease of supply voltage.…”

Section: Introductionmentioning

confidence: 99%

A 8-bit, 1-GHz coarse-fine time-based ADC with split-CDAC residue transfer

Wan

Bao

Jin

et al. 2022

IEICE Electron. Express

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This letter proposed a coarse-fine two stages time-based analogto-digital converter (TBADC). The coarse 4-bit TBADC is pipelined with the fine 5-bit TBADC for high conversion rate. There is one bit redundancy to tolerate the gain and offset mismatch between the coarse and fine stages. The residue is transferred by splitting the capacitor array in a fully passive way, which is non-attenuated and consumes less power. The dynamic VTC in this design has a high linearity over a wide input range. The proposed ADC is designed in a 65-nm CMOS technology. It consumed 3.1 mW at 1 GHz and had a Walden figure of merit of 15.9 fJ/conversion step.

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The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4

Cited by 12 publications

References 6 publications

Evaluating the Energy Measurements of the IBM POWER9 On-Chip Controller

Evaluating the Energy Measurements of the IBM POWER9 On-Chip Controller

Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses

A 8-bit, 1-GHz coarse-fine time-based ADC with split-CDAC residue transfer

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