Testing the path delay faults of ISCAS85 circuit c6288

Qiu, Wangqi; Walker, D.M.H.

doi:10.1109/mtv.2003.1250258

Cited by 5 publications

(2 citation statements)

References 18 publications

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“…[0] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [1] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [2] 32'hffffd555 32'h00000000 32'hd5542aab 32'h00000000 4'b1010 4'b1101 [3] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [4] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [5] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [6] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [7] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [8] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [9] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [10] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 The other three bits, adj [1], adj [2], and adj [3], indicate whether the tally for PE1, PE2, and PE3, respectively is to be incremented or decremented. [3] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [4] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [5] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [6] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [7] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [8] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [9] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 [10] 32'h00000000 32'h00000000 32'h00000000 32'h00000000 4'b0000 4'b0111 Fault coverage was evaluated iteratively by cycling through each fault node in the data table to check for incorrect results. There were 17 SA0 fault nodes in which no erroneous results were observed for any of the 1,200 pseudorandom input patterns.…”

Section: Operational Verification Of the Designmentioning

confidence: 99%

A Fault-Tolerant Alternative to Lockstep Triple Modular Redundancy

Baldwin¹

2000

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Section: Operational Verification Of the Designmentioning

confidence: 99%

A Fault-Tolerant Alternative to Lockstep Triple Modular Redundancy

Baldwin¹

2000

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“…Thus, larger number of tests would be necessary to ensure quality. Figure 1 shows a full adder, used extensively in the c6288 multiplier circuit of ISCAS85 combinational benchmarks [22]. A falling transition at the carryin input, C in , is non-robustly sensitized to the carryout output, C out , along the path C in , g 1 , C out .…”

Section: Introductionmentioning

confidence: 99%

Delay Test Quality Evaluation Using Bounded Gate Delays

Bose

Agrawal

2007

25th IEEE VLSI Test Symposium (VTS'07)

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Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are invalidated by hazards caused primarily due to non-zero delays of off-path circuit elements. Thus, non-robust tests are of limited value when process variations change gate delays. We propose a bounded gate delay model for test quality evaluation and give a novel simulation algorithm that is less pessimistic than previous approaches. The key idea is that certain time-correlations among the multiple transitions at the inputs of a gate cannot cause hazard at its output. We maintain "ambiguity lists" for gates. These are propagated with events, similar to fault lists in a traditional concurrent fault simulation. They are used to suppress erroneous unknown states. Experimental results for ISCAS benchmarks with gate delay variation of ±14% show a miscorrelation of critical path delay as much as 20%.

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