Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

Abstract

Application-specific integrated circuits (ASICs) are used in space-borne instruments for signal processing and detector readout. The electrical interface of these ASICs to frontend printed circuit boards is commonly accomplished with wire bonds. Through silicon via (TSV) technology has been proposed as an alternative interconnect technique that will reduce assembly complexity of ASIC packaging by replacing wire bonding with flip-chip bonding. TSV technology is advantageous in large detector arrays where TSVs enable close detector tiling on all sides. Wafer-level probe card testing of TSV ASICs is frustrated by solder balls introduced onto the ASIC surface for flip-chip bonding that hamper alignment. Therefore, we developed the ASIC test stand (ATS) to enable rapid screening and characterization of individual ASIC die. We successfully demonstrated ATS operation on ASICs originally developed for CdZnTe detectors on the Nuclear Spectroscopic and Telescope Array (NuSTAR) mission that were later modified with TSVs in a via-last process. We tested both backside blind-TSVs and frontside through-TSVs, with results from internal test pulser measurements that demonstrate performance equal to or exceeding the probe card wafer-level testing data. The ATS can easily be expanded or duplicated to parallelize ASIC screening for large area imaging detectors of future space programs.

Tuning of nuclear spectroscopic telescope array application specific integrated circuits to improve low energy threshold of future hard x-ray imaging detectors

“…TSV-NuASICs for HREXI enables flip-chip bonding each DCA to the PCB in tightly packed detector spacing. 14 readout lines routed through the NuASIC's silicon substrate to its back surface through a via-last process. 16 This TSV-enabled design will ultimately improve instrument integration by replacing the previously required 87 individual wire bonds per detector with a simpler and more robust flip-chip bonding process.…”

“…To probe a "bare" unattached TSV-NuASIC, we have designed and built an ASIC test stand (ATS) for control and data readout that contacts the device using an array of micropogo probes. 14,17 We utilize the NuASIC's internal test pulser to simulate fixedenergy x-ray events in each pixel channel and to determine the impact of NuASIC parameter adjustments.…”

“…For HREXI, each NuASIC will have the option of either using 87 TSVs or wirebonds. TSV-NuASICs for HREXI enables flip-chip bonding each DCA to the PCB in tightly packed detector spacing 14 …”

“…This TSV-enabled design will ultimately improve instrument integration by replacing the previously required 87 individual wire bonds per detector with a simpler and more robust flip-chip bonding process. To probe a “bare” unattached TSV-NuASIC, we have designed and built an ASIC test stand (ATS) for control and data readout that contacts the device using an array of micropogo probes 14 , 17 . We utilize the NuASIC’s internal test pulser to simulate fixed-energy x-ray events in each pixel channel and to determine the impact of NuASIC parameter adjustments.…”

“…(b) Computer-aided design model of the HREXI-coded aperture CZT/NuASIC detector plane, composed of tiled arrays of 2 × 2 detector crystal arrays (DCA).For HREXI, each NuASIC will have the option of either using 87 TSVs or wirebonds. TSV-NuASICs for HREXI enables flip-chip bonding each DCA to the PCB in tightly packed detector spacing 14.…”