Testing of Vega2, a chip multi-processor with spare processors.

Makar, S.; Altinis, T.; Patkar, N.; Wu, Jen-Ming

doi:10.1109/test.2007.4437584

Cited by 29 publications

(18 citation statements)

References 6 publications

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“…For example, while the Cell processor contains eight Synergistic Processing Elements (SPEs), Sony's PlayStation 3 video game console considers using only seven of them to increase the manufacturing yield [8]. This approach is also applied in Sun's UltraSPARC T1 processor [13], [14] and Azul's Vega2 chip [15].…”

Section: A Core-level Redundancy In Homogeneous Manycore Processorsmentioning

confidence: 99%

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Zhang

Han

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.

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Section: A Core-level Redundancy In Homogeneous Manycore Processorsmentioning

confidence: 99%

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Zhang

Han

et al. 2009

IEEE Trans. VLSI Syst.

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“…Using a broadcast-based TAM to test all of the cores in parallel has been described previously. The AZSCAN architecture tests multiple identical cores in parallel, and the responses are compared with the expected data in the chip [3]. A pipelinebased TAM allows for a great deal of flexibility in test applications, and the pipelining helps to improve test times and to reduce the capture power requirements [4].…”

Section: Introductionmentioning

confidence: 99%

“…Fig. 1 (b) shows a simple diagram of a typical parallel TAM architecture with on-chip comparator [3]. The test response data of multiple identical cores are compared with the expected data in the chip and if any differences appear, 1-bit data '1' will be recorded in sticky-bit registers (grey blocks in Fig.…”

Section: Introductionmentioning

confidence: 99%

A novel test access mechanism for parallel testing of multi-core system

Han

Choi

Kang

2014

IEICE Electron. Express

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“…The responses of the two cores are compared internally and the mismatch is reported by an external pin. In the AZSCAN architecture [11] , identical cores are tested by broadcasting the same test inputs to all of them. The responses of the cores are compared with the expect data which directly come from the external tester.…”

Section: Introductionmentioning

confidence: 99%

Design for Testability Features of Godson-3 Multicore Microprocessor

Liu

et al. 2011

J. Comput. Sci. Technol.

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This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

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Testing of Vega2, a chip multi-processor with spare processors.

Cited by 29 publications

References 6 publications

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

A novel test access mechanism for parallel testing of multi-core system

Design for Testability Features of Godson-3 Multicore Microprocessor

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