Testability analysis in high level data path synthesis

Steensma, J.; Geurts, Werner; Catthoor, Francky; Man, H. De

doi:10.1007/bf00971939

Cited by 17 publications

(1 citation statement)

References 15 publications

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“…The measures are calculated on the basis of circuit structures [1,9], functional/ behavioral levels [2,4,5,7,8,10], test sequence length [9], statistical analysis [3,6], information theoretic approaches [SI, or symbolic analysis [4,5]. These measures are mainly used as aides to test generation and/or design for testability.…”

Section: Introductionmentioning

confidence: 99%

Improving gate level fault coverage by RTL fault grading

Mao¹,

Gulati²

Proceedings International Test Conference 1996. Test and Design Validity

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A practical RTL level testability analysis methodology is presented in the papel: Both RTL models and functional veriJcation patterns are used in the RTL testability analysis. An RTL fault simulatol; which is the core of the methodology, is developed to support RTL testability analysis. It is able to generate quantitative RTL fault coverage and provide information for test pattem improvement to improve fault coverage and design modijcations to improve testability at the RTL level. Experimental results show that RTL fault coverage is quite close to fault coverage achieved at the gate level when designs are completed and mapped to a technology library. The results also show that effort to improve fault coverage at the RTL level very likely results in corresponding improvement of fault coverage at the gate level. Investigation of some of the causes of direrenee between RTL fault coverage and actual gate level fault coverage is also reported in the papel:INTERNATIONAL TEST CONFERENCE 0-7803-3540-6/96 $5.00 Q 1996 IEEE

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