Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs

Noia, Brandon; Chakrabarty, Krishnendu; Xie, Yuan

doi:10.1109/iccd.2009.5413172

Cited by 45 publications

(19 citation statements)

References 14 publications

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“…A solution to test access during post-bond test is a 3D DfT architecture based on wrappers [23] and dedicated scan registers between TSVs and tier logic gates [24], as depicted in Figure 1. 3D test can be further enhanced by exploring current 3D DFT architecture and generating input test patterns to screen TSV induced SDFs.…”

Section: Related Workmentioning

confidence: 99%

Timing-aware ATPG for critical paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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International audienceThrough-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools

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Section: Related Workmentioning

confidence: 99%

Timing-aware ATPG for critical paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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“…Previous work is mainly confined to the traditional 2D (Two Dimensional) Integrated Chip [1][2][3][4][5][6][7][8][9] with the appearance of 3D (Three-Dimensional) Integrated Chip, design based on the embedded IP core would become a popular style for 3D integrated chip, there is an urgent need to study the design for testability methodologies and optimization problems of 3D SoC. 3D Integrated Chips overcome the shortcoming of 2D integrated chip, which is the rapid growth of internal wiring length caused by the increase of circuits size; therefore it would improves the performance of integrated circuits.…”

Section: Introductionmentioning

confidence: 99%

“…B.Noia and K.Chakrabarty proposed a model based on integer linear programming algorithm [3]. The minimum goal of test time is achieved under the constraint condition of the finite TSV available.…”

Section: Introductionmentioning

confidence: 99%

Three-dimension Test Wrapper Design based on Multi-objective Cuckoo Search

Zhu¹,

Xu²,

Wu³

et al. 2015

TOCSJ

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Abstract:The main methodologies and recent patents on test wrapper design have been reviewed in this paper. The design of three-dimension test wrapper for IP module in System on Chip is a NP Hard problem. As the test time of an IP module is determined by the longest wrapper scan chain and each TSV has area costs and is a potential source of defects, it is necessary to shorten the longest wrapper chain and use less TSV. The paper proposes MOCS (Multi-Objective Cuckoo Search) algorithm to achieve the purpose of minimization of the IP module test time and the number of TSV used. The proposed algorithm, which is based on swarm intelligence, through levy flight operation and discovery rate, can achieve balance of the wrapper scan chains and use less TSV. Typical IP modules in ITC'02 benchmarks are used to prove the effectiveness of the proposed algorithm. Experimental results show that the algorithm can get better Pateto solutions Set, compared with NSGAII, and can reduce the test cost.

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“…Heuristic methods for designing core wrappers in 3D-SICs were developed in [14]. These methods do not address the problem of 3D TAM design.…”

Section: D Test Architecture and Test Schedulingmentioning

confidence: 99%

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Noia

Chakrabarty

2014

Self Cite

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As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects have become the dominant contributor to circuit delay and a significant component of power consumption. In order to reduce the length of these interconnects, 3D integration and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry. 3DSICs not only have the potential to reduce average interconnect length and alleviate many of the problems caused by long global interconnects, but they can offer greater design flexibility over 2D ICs, significant reductions in power consumption and footprint in an era of mobile applications, increased on-chip data bandwidth through delay reduction, and improved heterogeneous integration.Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a die stack, are a source of additional and unique defects not seen before in ICs. At the same time, testing these TSVs, especially before die stacking, is recognized as a major challenge.The testing of a 3D stack is constrained by limited test access, test pin availability, power, and thermal constraints. Therefore, efficient and optimized test architectures are needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively expensive.Methods of testing TSVs prior to bonding continue to be a difficult problem due to test access and testability issues. Although some built-in self-test (BIST) techniques have been proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through iv TSV probing. This has the benefit of not needing large analog test components on the die, which is a significant drawback of many BIST architectures. Coupled with an optimization method described in this dissertation to create parallel test groups for TSVs, test time for pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.The addition of boundary registers on functional TSV paths required for pre-bond probing results in an increase in delay on inter-die functional paths. This cost of test architecture insertion can be a significant drawback, especially considering that one benefit of 3D integration is that critical paths can be partitioned between dies to reduce their delay. This dissertation derives a retiming flow that is used to recover the additional delay added to TSV paths by test cell insertion.Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary during 3D-SIC manufacturing. To reduce test cost, the test architecture and test scheduling for the stack must be optimized to reduce test time across all necessary test insertions. This dissertation exam...

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Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs

Cited by 45 publications

References 14 publications

Timing-aware ATPG for critical paths with multiple TSVs

Timing-aware ATPG for critical paths with multiple TSVs

Three-dimension Test Wrapper Design based on Multi-objective Cuckoo Search

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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