Test volume and application time reduction through scan chain concealment

On compacting test response data containing unknown values

“…Methods to reduce test application time include generation of compact tests [1,2] and the use of multiple scan chains [3]. Methods to reduce tester storage requirements include methods to reduce test input data volume [4][5][6][7][8][9][10][11] and methods to reduce test response data volume [3,6,[12][13][14][15][16][17]. Some of these methods [6,13,14,16,17] address unknown values in the output response of the circuit.…”

On combining pinpoint test set relaxation and run-length codes for reducing test data volume

“…The column of "nonpinpoint" shows the results without using the gain table, i.e., the procedure tries to change all 1s in the test set to 0s without notice. The following columns gives results of EFDR coding [9], variable-length Huffman coding [14], RESPIN++ [15], and XOR network [12]. For many circuits, the proposed method showed the highest performance on compression.…”

“…Large test data volumes lead to an increase in testing time and the need for multiple ATE channel reloads, either from workstations across a network or from slow hard disks. As a result, a number of techniques have recently been presented in the literature to reduce test data volume, and thereby reduce test cost [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. One such technique is test compaction, which relies on ATPG techniques to generate a small test set with maximum fault coverage [1,2,3].…”

“…The decompression hardware for these methods consists of a sequential circuit implementing a finite state machine. Test compression methods that use a combinational circuit as a decompressor have also been proposed in the literature [12,13]. Finally, a number of methods using an embedded processor for software-based decompression have been proposed, e.g.…”

Virtual compression through test vector stitching for scan based designs

“…Bayraktaroglu and Orailoglu discuss a compression approach [4] that exploits the unspecified bits of test vectors and applies compressed test vectors into the circuit. The long scan chain is broken into multiple shorter partitions, while a decompression network either on the circuit under test or on the ATE is used to decode test vectors to the multiple scan chain partitions.…”